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| 型号： | IR3637STRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 11/21页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 440kHz |
| 占空比： | 85% |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 配用： | IRPP3637-12A-ND - KIT REF DES 12A 1PH SYNC BUCK IRDC3637-ND - BOARD EVAL SYNC BUCK REGULATOR |
| 其它名称： | IR3637STRPBFDKR |
IR3637SPBF
6) Place second pole at the ESR zero.
F P2 = F ESR
Layout Consideration
The layout is very important when designing high fre-
R 8 =
1
2 π × C 10 × F P2
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
Check if R 8 >
1
g m
less than expected results.
Start to place the power components, make all the con-
nection in the top layer with wide, copper filled areas.
× R 6
If R 8 is too small, increase R 7 and start from step 2.
7) Place second zero around the resonant frequency.
F Z2 = F LC
1
R 6 = - R 8
2 π × C 10 × F Z2
8) Use equation (1) to calculate R 5 .
V REF
R 5 =
V OUT - V REF
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to -
12dB). The phase margin should be greater than 45 for
overall stability.
Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
the ESR replace the single input capacitor with two par-
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir-
cuit ground (analog ground), to which all signals are ref-
erenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
Compensator
Type
Type II (PI)
Type III (PID)
Method A
Type III (PID)
Location of Zero
Crossover Frequency
(F O )
F LC < F ESR < F O < f S /2
F LC < F O < F ESR < f S /2
F LC < F O < f S /2 < F ESR
Typical
Output
Capacitor
Electrolytic,
Tantalum
Tantalum,
Ceramic
Ceramic
Method B
Table - The compensation type and location of zero
crossover frequency.
Detail information is dicussed in application Note AN-
1043 which can be downloaded from the IR Web-Site.
All design should be tested for stability to verify the cal-
culated values.
Rev. 1.1
06/16/05
www.irf.com
11
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| IR3638STRPBF | 功能描述:电压模式 PWM 控制器 HI FREQ SYNC PWM 400kHz 0.6V Track RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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