参数资料
型号: IR3640MTRPBF
厂商: International Rectifier
文件页数: 9/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-MLPQ
标准包装: 3,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.65MHz
占空比: 92%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 带卷 (TR)
IR3640MPBF
Circuit Description
THEORY OF OPERATION
Introduction
The IR3640 uses a PWM voltage mode control
scheme with external compensation to provide
good noise immunity and maximum flexibility in
selecting inductor values and capacitor types.
The switching frequency is programmable from
250kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3640 provides precisely regulated output
voltage programmed via two external resistors
from 0.7V to 0.9*Vin.
The IR3640 operates with an external bias
supply from 4.5V to 5.5V, allowing an extended
operating input voltage range from 1.5V to 24V.
The device utilizes the on-resistance of the low
side MOSFET as current sense element, this
method enhances the converter’s efficiency and
reduces cost by eliminating the need for external
current sense resistor .
Under-Voltage Lockout and POR
The under-voltage lockout circuit monitors the
input supply Vcc and the Enable input. It assures
that the MOSFET driver outputs remain in the off
state whenever either of these two signals drop
below the set thresholds. Normal operation
resumes once Vcc and Enable rise above their
thresholds.
The POR (Power On Ready) signal is generated
when all these signals reach the valid logic level
(see system block diagram). When the POR is
asserted the soft start sequence starts (see soft
start section).
Enable
The Enable features another level of flexibility for
start up. The Enable has precise threshold which
is internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3640 will turn on
only when the voltage at the Enable pin exceeds
this threshold, typically, 1.2V.
06/15/2009
If the input to the Enable pin is derived from the
bus voltage by a suitably programmed resistive
divider, it can be ensured that the IR3640 does
not turn on until the bus voltage reaches the
desired level. Only after the bus voltage reaches
or exceeds this level will the voltage at Enable
pin exceed its threshold, thus enabling the
IR3640. Therefore, in addition to being a logic
input pin to enable the IR3640, the Enable
feature, with its precise threshold, also allows the
user to implement an Under-Voltage Lockout for
the bus voltage V in . This is desirable particularly
for high output voltage applications, where we
might want the IR3640 to be disabled at least
until V in exceeds the desired output voltage level.
Fig. 3a: Normal Start up, Device turns on
when the Bus voltage reaches 10.2V
Figure 3b shows the recommended start-up
sequence for the non-sequenced operation of
IR3640, when Enable is used as a logic input.
Fig. 3b: Recommended startup sequence,
Non-Sequenced operation
9
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