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参数资料
| 型号： | IR3651STRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 14-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 460kHz |
| 占空比： | 80% |
| 电源电压： | 4.5 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 配用： | IRDC3651-ND - KIT REF DESIGN SYNCH BUCK REG |
IR3651SPBF
Feedback Compensation
The IR3651 is a voltage mode controller; the
The ESR zero of the output capacitor is
expressed as follows:
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
V O
F ESR =
1
2 ? π * ESR * C o
- -(12)
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45 o ).
The output LC filter introduces a double pole, –
R 8
R 9
Fb
V REF
E/A
Comp
C 4
R 3
Ve
C POLE
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180 o
(see figure 11). The resonant frequency of the LC
filter expressed as follows:
Gain(dB)
H(s) dB
F LC =
1
2 ? π L o ? C o
- -(11)
F Z
Frequency
Figure 11 shows gain and phase of the LC filter.
Since we already have 180 o phase shift just from
the output filter, the system risks being unstable.
Fig. 12: TypeII compensation network
and its asymptotic gain plot
The transfer function (Ve/Vo) is given by:
H ( s ) = ? ? g m *
R 9 ? 1 + sR 3 C 4
R 9 + R 8 ? ?
Gain
0dB
Phase
0
?
?
? *
sC 4
- -(13)
-40dB/decade
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
[ H ( s ) ] = ? ? ? g
? * R 3
R 9 + R 8 ? ?
F z =
- -(14)
-180
F LC Frequency F LC Frequency
Fig. 11: Gain and Phase of LC filter
The IR3651’s error amplifier is a differential-input
transconductance amplifier. The output is
available for DC gain control or AC phase
compensation.
R 9 ?
m *
?
1
2 π * R 3 * C 4
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-crossover frequency
The error amplifier can be compensated either in
typeII or typeIII compensation. When it is used in
typeII compensation the transconductance
(Fo):
F o > F ESR and F o ≤ ( 1/5 ~ 1/10 ) * F s
properties of the error amplifier become evident
Use the following equation to calculate R4:
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
R 3 =
V osc * F o * F ESR * ( R 8 + R 9 )
V in * F LC 2 * R 9 * g m
- -(15)
figure 12.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
06/08/2011
Where:
V in = Maximum Input Voltage
V osc = Oscillator Ramp Voltage
F o = Crossover Frequency
F ESR = Zero Frequency of the Output Capacitor
F LC = Resonant Frequency of the Output Filter
R 8 and R 9 = Feedback Resistor Dividers
g m = Error Amplifier Transconductance
15
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