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参数资料
| 型号： | IR3710MTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-MLPQ |
| 标准包装： | 3,000 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 3 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 16-MLPQ |
| 包装： | 带卷 (TR) |
IR3710MTRPBF
FUNCTIONAL DESCRIPTION
Refer to Block Diagram
ON-TIME GENERATOR
The PWM comparator initiates a SET signal (PWM
pulse) when the FB pin falls below lower of the
reference (VREF) or soft start (SS) voltage.
The PWM on-time duration is programmed with an
external resistor (R FF ) from the input supply (V IN ) to
the FF pin. The simplified equation for R FF is shown
in the equation 1. The FF pin is held to an internal
reference after EN goes HIGH. A copy of the current
in R FF charges a timing capacitor, which set the on-
time duration, as shown in equation 2.
An adaptive dead time prevents the simultaneous
conduction of the upper and lower MOSFETs. The
lower gate voltage must be below approximately 1V
after PWM goes HIGH before the upper MOSFET
can be gated on. Also the upper gate voltage, the
difference voltage between UGATE and PHASE,
must be below approximately 1V after PWM goes
LOW and before the lower MOSFET can be gated
on.
Diode emulation is enabled after PGOOD = HIGH
when FCCM is LOW. The control MOSFET is gated
on after the adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the adaptive
delay for PWM = LOW. The lower MOSFET is driven
‘off’ when the signal Z CROSS indicates that the inductor
current reverses as detected by the PHASE voltage
R FF =
T ON =
V OUT
1 V ? 20 pF ? F SW
R FF ? 1 V ? 20 pF
V IN
(1)
(2)
crossing the zero current threshold. The synchronous
MOSFET stays ‘off’ until the next PWM falling edge.
When FCCM = HIGH, forced continuous current
condition is selected. The control MOSFET is gated
on after the adaptive delay for PWM = HIGH and the
SOFT START
An internal 10uA current source charges external
capacitor on the SS pin to set the output voltage slew
rate during the soft start interval. The output voltage
reaches regulation when the FB pin is above the
under voltage threshold and the UV# = HIGH. Once
the voltage on the SS pin is above the PGOOD delay
threshold, the combination of the SSDelay and UV#
signals release the PGOOD pin. With EN = LOW, the
capacitor voltage and SS pin is held to the FB pin
voltage.
OVER CURRENT MONITOR
IR3710 monitors the output current every switching
cycle. The voltage across the synchronous
MOSFET, V PHASE is monitored for over current and
zero crossing. The minimum LGATE interval allows
time to sample V PHASE .
The over current trip point is programmed with a
resistor from ISET to PHASE pins, as shown in
equation 3. When over current is detected, output
gates are tri-state and SS voltage is pulled to 0V. A
new soft start cycle begins right after. If there is three
(3) consecutive OC events, IR3710 will disable
switching. Toggling VCC or EN will allow next start
up.
synchronous MOSFET is gated on after the adaptive
delay for PWM = LOW.
The synchronous MOSFET gate is driven on for a
minimum duration. This minimum duration allows
time to recharge the bootstrap capacitor and allows
the current monitor to sample the phase voltage.
CONTROL LOGIC
The control logic monitors input power sources for
supply voltage conditions, sequences the converter
through the soft-start and protective modes, and
indicates output voltage status on the PGOOD pin.
VCC and PVCC pins are continuously monitored.
IR3710 is disabled if either of these voltages drops
below falling thresholds.
IR3710 will initiate a soft start when the VCC and
PVCC are in the normal range and the EN pin =
HIGH. In the event of a sustained overload, a
counter keep track of 4 consecutive soft-start cycles
and disables IR3710.
If the overload is momentary and output voltage is
within regulation before 4 consecutive soft-start
cycles, PGOOD transitions HIGH to reset the
counter.
OVER VOLTAGE PROTECTION
R SET =
R DSON ? I OC
20 μ A
(3)
IR3710 monitors the voltage at FB node. If the FB
voltage is above the threshold of over voltage, the
gates are turn off and pulls PGOOD signal low.
GATE DRIVE LOGIC
The gate drive logic features adaptive dead time,
diode emulation, and a minimum lower gate interval.
Toggling VCC or EN will allow next start up.
Page 11 of 20
www.irf.com
IR Confidential
4/26/10
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