参数资料
型号: IR3853MTR1PBF
厂商: International Rectifier
文件页数: 15/35页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A PQFN17
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
标准包装: 1
系列: SupIRBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.7 V ~ 18.9 V
输入电压: 1.5 V ~ 21 V
PWM 型: 电压模式
频率 - 开关: 225kHz ~ 1.65MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-PowerVQFN
包装: 标准包装
供应商设备封装: 17-PQFN(4x5)
其它名称: IR3853MTR1PBFDKR
PD-97516
IR3853MPbF
Thermal Shutdown
Temperature sensing is provided inside IR3853.
The trip threshold is typically set to 140 o C. When
1.5V <Vin<16V
4.5V <Vcc<5.5V
trip threshold is exceeded, thermal shutdown
turns off both MOSFETs and discharges the soft
start capacitor.
PGood
Vcc
PGood
Enable
Vin
Boot
SW
OCSet
RA
Vo(master)
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20 o C hysteresis in the thermal
Seq
Rt
SS/ SD
Gnd
PGnd
Fb
Comp
RB
shutdown threshold.
1.5V <Vin<16V
Output Voltage Sequencing
The IR3853 can accommodate user
4.5V <Vcc<5.5V
programmable sequencing options using Seq,
Enable and Power Good pins.
Vo(master)
Vcc
Enable
Vin
Boot
SW
Vo(slave)
PGood
RE
PGood
Seq
OCSet
Fb
RC
Vo1
RF
Rt
RD
SS/ SD
Gnd
PGnd
Comp
Vo2
Simultaneous Powerup
Fig. 8a. Simultaneous Power-up of the slave
with respect to the master.
Through these pins, voltage sequencing such as
simultaneous and sequential can be
implemented. Figure 8. shows simultaneous
sequencing configurations. In simultaneous
power-up, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
R E /R F =R C /R D , therefore, the output voltage of
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
Rev 4.0
Fig. 8b. Application Circuit for Simultaneous
Sequencing
Power-Good and Over-voltage Protection
The V sns pin forms an input to a window
comparator whose upper and lower thresholds
are 0.805V and 0.595V, respectively. Hence, the
Power Good signal is flagged when the V sns pin
voltage is within the PGood window, i.e.
between 0.595V to 0.805V, as shown in figure 9.
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. Figure 9a shows the
PGood timing diagram for non-tracking
operation. In this case, during startup, PGood
goes high after the SS voltage reaches 2.1V if
the Vsns voltage is within the PGood
comparator window. Figure 9.a and Figure 9.b
also show a 256 cycle delay between the Vsns
voltage entering within the thresholds defined by
the PGood window and PGood going high.
If the output voltage exceeds the over voltage
threshold, an over voltage trip signal asserts, this
will result to turn off the high side driver and turn
on the low side driver until the Vsns voltage
drops below 1.15*Vref threshold. Both drivers are
latched off until a reset performed by cycling
either Vcc or Enable.
The OVP threshold can be externally
programmed to user defined value. Figure 10
shows the response in over-voltage condition.
15
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