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参数资料
| 型号： | IR5001STRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | IC CTLR/MOSFET UNIV N-CH 8-SOIC |
| 标准包装： | 1 |
| 应用： | -48V Dist 电源系统，AdvancedTCA ? 系统 |
| FET 型： | N 沟道 |
| 输出数： | 1 |
| 内部开关： | 无 |
| 延迟时间 - 开启： | 27µs |
| 延迟时间 - 关闭： | 130ns |
| 电源电压： | 36 V ~ 75 V |
| 电流 - 电源： | 500µA |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 其它名称： | IR5001STRPBFDKR |
IR5001S & (PbF)
PARAMETERS
SYMBOL
TEST CONDITION
MIN TYP MAX UNITS
Output Section
High Level Output Voltage
Low Level Output Voltage
Turn-On DelayTime
Rise Time
Turn-Off Delay Time
Fall Time
Vout HI
Vout LO
td(on)
tr
td(off)
tf
Vline=25V, IOH=50uA,
V(INN)=-0.3V
IOL=100mA, V(INN)=+0.3V
Vout switching from LO to HI, Fig.5
Vout switching from HI to LO, Fig.5
10.2 11.5 14.1
0.1
5 27 45
0.09 0.7 1
110 130 170
10 26 39
V
V
us
ms
ns
FETch and FETst
FETch Sink Current
FETch Output Delay Time
I(FETch)
FETch_pd
FETch=5V
Note 1
-0.5 -1.1
0.8
-2
1.8
uA
us
FETch Threshold
Vth(FETch)
0.9
1.2
1.5
V
5k resistor from FETst to 5V logic bias.
FETst Threshold Voltage
Vth(FETst)
V(INP) = Gnd, V(INN) ramping down
-525 -300 -200
mV
from 0 until FETst switches to Low.
FETst Low Level Output
Voltage
VOL
Isink=1mA, V(INN)=-0.5V
0
50
100
mV
Note 1: Guaranteed by design but not tested in production.
Note 2: Low Vcc output voltage corresponds to low UVLO voltage
PIN DESCRIPTIONS
PIN#
1
2
3
4
5
6
7
8
www.irf.com
PIN SYMBOL
Vline
Vcc
FETch
FETst
INP
INN
Gnd
Vout
PIN DESCRIPTION
IC power supply pin for 36V to 75V input communications systems.
Minimum 25V has to be applied at this pin to bias the IC.
Output pin of the internal shunt regulator, or input pin for biasing the IC via
external resistor. This pin is internally regulated at 12.5V typical. A
minimum 0.1uF capacitor must be connected from this pin to Gnd of IR5001.
FET check input pin. Together with FET status output pin, the FETch pin
can be used to determine the state of the Active ORing circuit and power
system redundancy.
FET status output pin. Together with FETch input pin, the FETst pin can be
used to determine the state of the Active ORing circuit and power system
redundancy.
Positive input of internal comparator. This pin should connect to the source
of N-channel Active ORing MOSFET.
Negative input pin of internal comparator. This pin should connect to the
drain of N-channel Active ORing MOSFET.
Ground pin of the IR5001.
Output pin for the IR5001. This pin is used to directly drive the gate of the
Active Oring N-Channel MOSFET.
3
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相关代理商/技术参数 |
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|---|---|
| IR5001STRPBF-CUT TAPE | 制造商:IR 功能描述:IR5001 Series 9.6 V 3 A 130 ns Universal Active ORing Controller - SOIC-8 |
| IR5002 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | BJT | DARLINGTON | NPN | 500V V(BR)CEO | 15A I(C) | TO-3 |
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