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XMEGA A [MANUAL]
8077I–AVR–11/2012
4.8.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
4.9
External Memory
Up to four ports are dedicated to external memory, supporting external SRAM, SDRAM, and memory mapped
address space will always start at the end of internal SRAM.
4.10
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time. See
Figure 4-3 on page 23.
Figure 4-3.
Bus access.
4.10.1 Bus Priority
When several masters request access to the same bus, the bus priority is in the following order (from higher to lower
priority):
1.
Bus Master with ongoing access.
Bus access granted, but waiting for slave to complete
2.
Bus Master with ongoing burst.
If DMA controller is transferring between two locations within the same memory section the read and write master
will alternate until the burst is complete.
3.
Bus Master requesting new burst access.
1st pri: CPU (CALL/RET)
2nd pri: DMAC (2BYTE or more)
4.
Bus Master requesting new bus access.
1st pri: CPU (load, store)
2nd pri: 2 DMAC (1BYTE)
Peripherals and system modules
Bus matrix
CPU
DMA
RAM
DAC
OCD
USART
SPI
Timer /
Counter
TWI
Interrupt
Controller
Power
Management
SRAM
External
Programming
External
Memory
EBI
PDI
AVR core
CH0
ADC
AC
Crypto
modules
Event System
Controller
Oscillator
Control
CH1
CH2
CH3
Non-Volatile
Memory
EEPROM
Flash
Real Time
Counter
I/O
NVM
Controller
Battery
Backup