参数资料
型号: IRS23364DSTRPBF
厂商: International Rectifier
文件页数: 33/49页
文件大小: 0K
描述: IC GATE DRIVER HV 3PHASE 28-SOIC
标准包装: 1
配置: 3 相桥
输入类型: 差分
延迟时间: 530ns
电流 - 峰: 200mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 600V
电源电压: 11.5 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 标准包装
产品目录页面: 1382 (CN2011-ZH PDF)
其它名称: IRS23364DSTRPBFDKR
IRS2336x(D) Family
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
34). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops
must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT
collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a
voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 34: Antenna Loops
Supply Capacitor:
It is recommended to place a bypass capacitor (C IN ) between the V CC and V SS pins.
This
connection is shown in Figure 35. A ceramic 1 μF ceramic capacitor is suitable for most applications.
component should be placed as close as possible to the pins in order to reduce parasitic elements.
V cc
HIN (x3)
V B (x3)
LIN (x3)
HO (x3)
EN
This
FAULT
V S (x3)
C IN
RCIN
ITRIP
LO (x3)
V SS
COM
Figure 35: Supply capacitor
www.irf.com
33
? 2009 International Rectifier
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