参数资料
型号: IRS25411SPBF
厂商: International Rectifier
文件页数: 14/20页
文件大小: 0K
描述: IC LED CONS CURR CTRL 8SOIC
标准包装: 95
拓扑: PWM,降压(降压)
输出数: 1
内部驱动器:
类型 - 主要: 通用
频率: 500kHz
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
IRS254(0,1)(S)PbF
100
90
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20
Enable Duty Cycle Relationship to Light Output
to form the voltage clamp. The repetition of the
spikes can be reduced by simply increasing the
capacitor size.
The two resistors form a voltage divider for the
output, which is then fed into the cathode of the zener
diode. The diode will only conduct, flooding the
enable pin, when its nominal voltage is exceeded.
The chip will enter a disabled state once the divider
network produces a voltage at least 2.5 V greater
10
0
0
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20
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40
50
60
70
80
90
100
than the zener rating. The capacitor serves only to
filter and slow the transients/switching at the positive
EN
Percentage of Light Output
Fig.5 Light Output vs Enable Pin Duty Cycle
output terminal. The clamped output voltage can be
determined by the following analysis. The choice of
capacitor is at the designer’s discretion.
This scheme will not be adequate in all applications.
An improved method is described in IRPLLED1 Rev
D reference design documentation.
V out =
( 2 .5 V + DZ )( R 1 + R 2 )
R 2
HO
LO
Fig.6 IRS254(01,11) Dimming Signals
Open Circuit Protection Mode
DZ = Zener Diode Nominal Rated Voltage
There are several
methods of providing
over voltage protection
at the output if needed.
Vout
R1
The following very
simple method uses a
voltage divider,
capacitor, and zener
diode, the output
R2
IFB
EN
3
4
Fig.8 Open Circuit Fault Signals, with Clamp
voltage can be clamped
at any desired value. In open-
Fig.7 Open Circuit
Protection Scheme
Under-voltage Lock-out Mode
circuit condition without any
output clamp, the positive output terminal may reach a
high DC voltage. Switching will still occur between the
HO and LO outputs, whether due to the output voltage
clamp or the watchdog timer. Transients and switching
will be observed at the positive output terminal as seen
in Fig. 8. The difference in signal shape, between the
output voltage and the I FB , is due to the capacitor used
www.irf.com
14
The under-voltage lock-out mode (UVLO) is defined
as the state IRS254(01,11) is in when V CC is below
the turn-on threshold of the IC. During startup
conditions, if the IC supply remains below V CCUV+ , the
IRS254(01,11) will enter the UVLO mode. This state
is very similar to when the IC has been disabled via
control signals, except that LO is also held low.
When the supply is increased to V CCUV+ , the IC enters
? 2010 International Rectifier
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