参数资料
型号: IRU3146CFTR
厂商: International Rectifier
文件页数: 4/30页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 28TSSOP
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 345kHz
占空比: 85%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
包装: 剪切带 (CT)
产品目录页面: 1384 (CN2011-ZH PDF)
其它名称: *IRU3146CFTR
IRU3146CFCT
IRU3146
DEADBAND TIME
90%
High Side
Driver HD 2V
10%
Tr
Tf
Driver LD 2V
Low Side
90%
10%
Deadband
H_to_L
Tr
Tf
Deadband
L_to_H
Figure 2 - Deadband time definition.
T DB(TYP) =(Deadband H_toL+Deadband L_to -H)/2
PIN DESCRIPTIONS
PIN#
1
2
3
4
5,23
6,22
PIN SYMBOL
PGood
Vcc
V OUT3
Rt
V SEN2 , V SEN1
Fb2,Fb1
PIN DESCRIPTION
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC.
Output of the internal LDO.
Switching frequency setting resistor. (see Figure 10 for selecting resistor values).
Sense pins for OVP and PGood. For 2-Phase operation tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
7,21
Comp2, Comp1 Compensation pins for the error amplifiers.
These pins provide soft-start for the switching regulator. An internal current source charges
8
20
SS2 / SD
SS1 / SD
external capacitors that are connected from these pins to ground which ramp up the
output of the switching regulators, preventing them from overshooting as well as limiting
the input current. The converter can be shutdown by pulling these pins below 0.3V.
9,19
OCSet2,OCSet1 Current limit resistor (R LIM ) connection pins for output 1 and 2. The other ends of R LIM s are
connected to the corresponding switching nodes.
10,18
11,17
VcH2, VcH1
HDrv2, HDrv1
Supply voltage for the high side output drivers. These are connected to voltages that must
be typically 6V higher than their bus voltages. A 1 μ F high frequency capacitor must be
connected from these pins to GND to provide peak drive current capability.
Output drivers for the high side power MOSFETs. 1)
12,16
PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be connected
to the system’s ground plane.
13,15
14
24
25
LDrv2, LDrv1
V CL
Sync
Hiccup
Output drivers for the synchronous power MOSFETs.
Supply voltage for the low side output drivers. This pin should be high for normal operation
The internal oscillator may be synchronized to an external clock via this pin.
When pulled High, it puts the device current limit into a hiccup mode. When pulled Low,
the output latches off, after an overcurrent event.
4
www.irf.com
Rev. 1.1
6/25/04
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