参数资料
型号: IS61C64AL-10JLI
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 8K x 8 HIGH-SPEED CMOS STATIC RAM
中文描述: 8K X 8 STANDARD SRAM, 10 ns, PDSO28
封装: 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
文件页数: 5/13页
文件大小: 105K
代理商: IS61C64AL-10JLI
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IS61C64AL
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/16/06
5
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
Figure 2
480
Ω
5 pF
Including
jig and
scope
255
Ω
OUTPUT
5V
480
Ω
30 pF
Including
jig and
scope
255
Ω
OUTPUT
5V
Figure 1
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
Min.
-12 ns
Min. Max.
Symbol
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCS
(2)
t
HZCS
(2)
t
PU
(3)
t
PD
(3)
Parameter
Max
Unit
Read Cycle Time
10
12
ns
Address Access Time
10
12
ns
Output Hold Time
2
2
ns
CE
Access Time
10
12
ns
OE
Access Time
6
6
ns
OE
to Low-Z Output
0
0
ns
OE
to High-Z Output
5
6
ns
CE
to Low-Z Output
2
3
ns
CE
to High-Z Output
5
7
ns
CE
to Power-Up
0
0
ns
CE
to Power-Down
10
12
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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IS61C64AL-10TI 8K x 8 HIGH-SPEED CMOS STATIC RAM
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