- 您现在的位置：买卖IC网 > PDF目录299228 > IS61LPD51236A-200B3I (INTEGRATED SILICON SOLUTION INC) 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM PDF资料下载
参数资料
| 型号： | IS61LPD51236A-200B3I |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 36 CACHE SRAM, 3.1 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165 |
| 文件页数： | 13/29页 |
| 文件大小： | 552K |
| 代理商： | IS61LPD51236A-200B3I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/08/08
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
TaP INSTRUCTION SET
Eightinstructionsarepossiblewiththethree-bitinstruction
register and all combinations are listed in the Instruction
Codetable.Three instructions are listed as RESERVED
and should not be used and the other five instructions are
describedbelow.TheTAPcontrollerusedinthisSRAM
isnotfullycompliantwiththe1149.1conventionbecause
some mandatory instructions are not fully implemented.
TheTAPcontrollercannotbeusedtoloadaddress,dataor
control signals and cannot preload the Input or Output buf-
fers.TheSRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD;insteaditperformsacaptureoftheInputs and
Outputringwhentheseinstructionsareexecuted.Instruc-
tionsareloadedintotheTAPcontrollerduringtheShift-IR
statewhentheinstructionregisterisplacedbetweenTDI
andTDO.Duringthisstate,instructionsareshiftedfrom
theinstructionregisterthroughtheTDIandTDOpins.To
executeaninstructiononceitisshiftedin,theTAPcontrol-
lermustbemovedintotheUpdate-IRstate.
EXTEST
EXTESTisamandatory1149.1instructionwhichistobe
executedwhenevertheinstructionregisterisloadedwith
all0s.BecauseEXTESTisnotimplementedintheTAP
controller,thisdeviceisnot1149.1standardcompliant.
TheTAPcontrollerrecognizesanall-0instruction.Whenan
EXTESTinstructionisloadedintotheinstructionregister,
theSRAMrespondsasifaSAMPLE/PRELOADinstruction
hasbeenloaded.Thereisadifferencebetweentheinstruc-
tions, unlike the SAMPLE/PRELOADinstruction,EXTEST
placestheSRAMoutputsinaHigh-Zstate.
IDCODE
TheIDCODEinstructioncausesavendor-specific,32-bit
code to be loaded into the instruction register.It also places
the instruction register between theTDI andTDO pins
andallowstheIDCODEtobeshiftedoutofthedevice
when theTAP controller enters the Shift-DR state.The
IDCODEinstructionisloadedintotheinstructionregister
uponpower-uporwhenevertheTAPcontrollerisgivena
test logic reset state.
SaMPlE-Z
The SAMPLE-Z instruction causes the boundary scan
registertobeconnectedbetweentheTDIandTDOpins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
allSRAMoutputsintoaHigh-Zstate.
SaMPlE/PRElOaD
SAMPLE/PRELOADisa1149.1mandatoryinstruction.The
PRELOADportionofthisinstructionisnotimplemented,so
theTAPcontrollerisnotfully1149.1compliant.Whenthe
SAMPLE/PRELOADinstructionisloadedtotheinstruc-
tionregisterandtheTAPcontrollerisintheCapture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
ItisimportanttorealizethattheTAPcontrollerclockoper-
atesatafrequencyupto10MHz,whiletheSRAMclock
runsmorethananorderofmagnitudefaster.Becauseof
theclockfrequencydifferences,itispossiblethatduring
theCapture-DRstate,aninputoroutputwillunder-goa
transition.TheTAPmayattemptasignalcapturewhilein
transition(metastablestate).Thedevicewillnotbeharmed,
but there is no guarantee of the value that will be captured
or repeatable results.
Toguaranteethattheboundaryscanregisterwillcapture
thecorrectsignalvalue,theSRAMsignalmustbestabilized
longenoughtomeettheTAPcontroller’scaptureset-up
plus hold times (tcs and tch).ToinsurethattheSRAMclock
input is captured correctly, designs need a way to stop (or
slow)theclockduringaSAMPLE/PRELOADinstruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
Oncethedataiscaptured,itispossibletoshiftoutthedata
byputtingtheTAPintotheShift-DRstate.Thisplacesthe
boundaryscanregisterbetweentheTDIandTDOpins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-
DR state while performing a SAMPLE/PRELOAD instruction
willhavethesameeffectasthePause-DRcommand.
BYPaSS
When the BYPASS instruction is loaded in the instruc-
tionregisterandtheTAPisplacedinaShift-DRstate,
thebypassregisterisplacedbetweentheTDIandTDO
pins.TheadvantageoftheBYPASSinstructionisthatit
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
Theseinstructionsarenotimplementedbutarereserved
forfutureuse.Donotusetheseinstructions.
相关PDF资料 |
PDF描述 |
|---|---|
| IS61LPD51236A-200TQ | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51236A-200TQI | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51236A-200TQLI | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51236A-250B3 | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51236A-250B3I | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61LPD51236A-200B3I-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPD51236A-200B3-TR | 功能描述:静态随机存取存储器 18Mb 512Kx36 200MHz Sync 静态随机存取存储器 3.3v RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPD51236A-200TQ | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51236A-200TQI | 功能描述:静态随机存取存储器 18Mb 512Kx36 200MHz Sync 静态随机存取存储器 3.3v RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPD51236A-200TQI-TR | 功能描述:静态随机存取存储器 18Mb 512Kx36 200MHz Sync 静态随机存取存储器 3.3v RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。