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参数资料
| 型号： | IS61LPS51218A |
| 厂商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 256K × 36，为512k × 18 9 MB的同步流水线，单周期取消选择静态RAM |
| 文件页数： | 13/32页 |
| 文件大小： | 217K |
| 代理商： | IS61LPS51218A |
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20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI
pin on the rising edge of TCK and output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruc-
tion register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state
as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
is set LOW (VSS) when the BYPASS instruction is ex-
ecuted.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded to the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP
controller is in the Shift-DR state. The ID register has vendor
code and other information described in the Identification
Register Definitions table.
Scan Register Sizes
Register
Bit Size
Name
(x18)
(x36)
Instruction
3
Bypass
1
ID
32
Boundary Scan
75
IDENTIFICATION REGISTER DEFINITIONS
InstructionField
Description
256Kx36
512Kx18
RevisionNumber (31:28)
Reservedforversionnumber.
xxxx
DeviceDepth (27:23)
DefinesdepthofSRAM.256Kor512K
00111
01000
DeviceWidth (22:18)
Defines width of the SRAM. x36 or x18
00100
00011
ISSIDeviceID (17:12)
Reserved for future use.
xxxxx
ISSIJEDECID (11:1)
AllowsuniqueidentificationofSRAMvendor.
00011010101
IDRegisterPresence (0)
Indicate the presence of an ID register.
1
相关PDF资料 |
PDF描述 |
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| IS61LV6464-5PQ | 64K X 64 CACHE SRAM, 5 ns, PQFP128 |
| IS61QDB21M36-300M3 | 1M X 36 DDR SRAM, PBGA165 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61LPS51218A_12 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-200B2 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-200B2I | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-200B3 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS51218A-200B3I | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
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