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参数资料
| 型号： | IS61SP25618-5TQI |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | Octal Transparent D-Type Latches With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | 256K X 18 CACHE SRAM, 5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 15/15页 |
| 文件大小： | 120K |
| 代理商： | IS61SP25618-5TQI |
IS61SP25616
IS61SP25618
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
04/17/01
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-
166
-150
-133
-5
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX(3)
Clock Frequency
—
166
—
150
—
133
—
100
MHz
tKC(3)
Cycle Time
6
—
6.7
—
7.5
—
10
—
ns
tKH
Clock High Time
2.4
—
2.6
—
2.8
—
3
—
ns
tKL(3)
Clock Low Time
2.4
—
2.6
—
2.8
—
3
—
ns
tKQ(3)
Clock Access Time
—
3.5
—
3.8
—
4
—
5ns
tKQX(1)
Clock High to Output Invalid
3
—
3
—
3
—
3
—
ns
tKQLZ(1,2)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
ns
tKQHZ(1,2)
Clock High to Output High-Z
1.5
3.5
1.5
3.5
1.5
3.5
1.5
3.5
ns
tOEQ(3)
Output Enable to Output Valid
—
3.5
—
3.5
—
3.8
—
5ns
tOEQX(1)
Output Disable to Output Invalid
0
—
0
—
0
—
0
—
ns
tOELZ(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
ns
tOEHZ(1,2)
Output Disable to Output High-Z
2
3.5
2
3.5
2
3.8
2
5
ns
tAS(3)
Address Setup Time
2
—
2
—
2
—
2
—
ns
tSS(3)
Address Status Setup Time
2
—
2
—
2
—
2
—
ns
tWS(3)
Write Setup Time
2
—
2
—
2
—
2
—
ns
tCES(3)
Chip Enable Setup Time
2
—
2
—
2
—
2
—
ns
tAVS(3)
Address Advance Setup Time
2
—
2
—
2
—
2
—
ns
tAH(3)
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH(3)
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tWH(3)
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH(3)
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tAVH(3)
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
相关PDF资料 |
PDF描述 |
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| IS61SPD25632T | Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85 |
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| IS61VPS51218A-250B3 | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
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