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参数资料
| 型号： | IS66WVD409616ALL-7010BLI |
| 元件分类： | SRAM |
| 英文描述： | 4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54 |
| 封装： | 8 X 6 MM, MO-207, VFBGA-54 |
| 文件页数： | 17/52页 |
| 文件大小： | 1128K |
| 代理商： | IS66WVD409616ALL-7010BLI |
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IS66WVD409616ALL
Advanced Information
24
Rev.00A | January 2010
www.issi.com - SRAM@issi.com
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Latency codes from two
(three clocks) to six (seven clocks) and eight (nine clocks) are supported (see Tables 6
and 7, Figure 13, and Figure 14).
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency
counter. However, WAIT must be monitored to detect delays caused by collisions with
refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for
worst-case refresh collisions. The latency counter must be configured to match the
initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed
initial latency. The burst begins after the number of clock cycles configured by the
latency counter. (See Table 6 and Figure 13)
BCR
[13:11]
Latency
Configuration
Code
Latency
Max Input CLK Frequency (MHz)
Normal
Refresh
Collision
-75
-96
-12
010
2 (3 clocks)
2
4
66 (15.0ns)
52 (18.5ns)
011
3 (4 clocks)-default
3
6
104 (9.62ns)
80 (12.5ns)
100
4 (5 clocks)
4
8
133 (7.5ns)
others
Reserved
-
Table 6. Variable Latency Configuration Codes (BCR[14] = 0)
Notes:
1. Latency is the number of clock cycles from the initialization of a burst operation until data appears.
Data is transferred on the next clock cycle. READ latency can range from the normal latency to the value
shown for refresh collision.
ADQ0-
ADQ15
ADV#
CLK
VALID
OUTPUT
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
ADQ0-
ADQ15
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
ADQ0-
ADQ15
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
Code 2 (3 clocks)
Code 3 (4 clocks) : Default
Code 4 (5 clocks)
Figure 13. Latency Counter (Variable Latency, No Refresh Collision)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IS66WVE1M16ALL | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:1.8V Core Async/Page PSRAM |
| IS66WVE1M16ALL-70BLI | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:1.8V Core Async/Page PSRAM |
| IS66WVE1M16BLL | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:3.0V Core Async/Page PSRAM |
| IS66WVE1M16BLL-55BLI | 功能描述:静态随机存取存储器 16Mb 1M x 16 55ns Pseudo 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS66WVE1M16BLL-55BLI-TR | 功能描述:静态随机存取存储器 16Mb 1M x 16 55ns Pseudo 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
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