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参数资料
| 型号： | IS82C37A-5 |
| 厂商： | INTERSIL CORP |
| 元件分类： | DMA控制器 |
| 英文描述： | CMOS High Performance Programmable DMA Controller |
| 中文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 11/23页 |
| 文件大小： | 204K |
| 代理商： | IS82C37A-5 |
4-202
82C37A
Software Commands
There are special software commands which can be
executed by reading or writing to the 82C37A. These com-
mands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
Clear First/Last Flip-Flop -
This command is executed
prior to writing or reading new address or word count infor-
mation to the 82C37A. This command initializes the flip-flop
to a known state (low byte first) so that subsequent accesses
to register contents by the microprocessor will address
upper and lower bytes in the correct sequence.
Set First/Last Flip-Flop -
This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
Master Clear -
This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C37A will enter the idle cycle.
Clear Mask Register -
This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
Clear Mode Register Counter -
Since only one address
location is available for reading the Mode registers, an inter-
nal two-bit counter has been included to select Mode regis-
ters during read operation. To read the Mode registers, first
execute the Clear Mode Register Counter command, then
do consecutive reads until the desired channel is read. Read
order is channel 0 first, channel 3 last. The lower two bits on
all Mode registers will read as ones.
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
tor to V
CC
is required. The value of the external pull-up
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C37A will not accept
external EOP signals when it is in a SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C37A enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C37A is in an SI state.
CHANNEL
0
REGISTER
OPERATION
Write
SIGNALS
FIRST/LAST
FLIP-FLOP
STATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DATA
BUS
DB0-DB7
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
CS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOR
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
IOW
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Base and Current Address
Current Address
Read
Base and Current Word
Count
Current Word Count
Write
Read
1
Base and Current Address
Write
Current Address
Read
Base and Current Word
Count
Current Word Count
Write
Read
2
Base and Current Address
Write
Current Address
Read
Base and Current Word
Count
Current Word Count
Write
Read
3
Base and Current Address
Write
Current Address
Read
Base and Current Word
Count
Current Word Count
Write
Read
FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
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