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参数资料
| 型号： | ISB35279 |
| 厂商： | 意法半导体 |
| 英文描述： | HCMOS STRUCTURED ARRAY |
| 中文描述： | HCMOS结构化阵列 |
| 文件页数： | 1/15页 |
| 文件大小： | 345K |
| 代理商： | ISB35279 |
ISB35000 SERIES
HCMOS STRUCTURED ARRAY
PRELIMINARY DATA
FEATURES
0.5 micron triple layer metal HCMOS process
featuring retrograde well technology, low
resistance salicided active areas, polysilicide
gates and thin metal oxide.
3.3 V optimized transistor with 5 V I/O interface
capability
2 - input NAND delay of 0.210 ns (typ) with
fanout = 2.
Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
High drive I/O; capability of sinking up to 48 mA
with slew rate control, current spike suppression
and impedance matching.
Metallised generators to support SPRAM and
DPRAM, plus an extensive embedded function
library.
Combines Standard Cell Features with Sea of
Gates time to market.
May 1994
Fully independent power and ground
configurations for inputs, core and outputs.
Programmable I/O ring capability up to 1000
pads.
Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
Active pull up and pull down devices.
Buskeeper I/O functions.
Oscillators for wide frequency spectrum.
Broad range of 400 SSI cells.
300 element macrofunction library.
Design For Test includes LSSD macro library
option and IEEE 1149.1 JTAG Boundary Scan
architecture built in.
Cadence and Mentor based design system with
interfaces from multiple workstations.
Broad ceramic and plastic package range.
Latchup trigger current +/- 500 mA.
ESD protection +/- 4000 volts.
Internal
Device Name
Total Sites
1
Estimated
2
Gates
Total Usable
3
Gates
Maximum
4
Device Pads
Maximum
5
I/O
ISB35083
ISB35130
ISB35166
ISB35208
ISB35279
ISB35389
ISB35484
ISB35666
ISB35832
124,416
194,400
249,696
311,904
418,176
584,064
726,624
998,784
1,247,616
82,944
129,600
166,464
207,936
278,784
389,376
484,416
665,856
831,744
58,060
90,720
116,524
145,555
195,148
253,094
314,870
399,513
499,046
188
232
260
288
332
388
432
504
560
172
216
244
272
316
372
416
488
544
Notes :
1. Internal sites is based on the number of placement sites available to the route and place software
2. A factor of 1.5 is used to derive the gate complexity from the total available sites. This number is in Nand2 equivalents
3. Factors of 70%, 65%, and 60% have been used to calculate the routing efficiency. This number may vary depending on the
design.
4. 16 corner pads are dedicated to internal and external power supplies. I/O pads may be configured for additional power.
5. Maximum I/O = total device pads minus power pads.
Table 1. Product range
1/15
相关PDF资料 |
PDF描述 |
|---|---|
| ISB35000 | HCMOS STRUCTURED ARRAY |
| ISB35083 | HCMOS STRUCTURED ARRAY |
| ISB35130 | GT 31C 31#16 PIN PLUG |
| ISB35166 | GT 48C 48#16 PIN PLUG |
| ISB35208 | GT 48C 48#16 PIN PLUG |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISB35389 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:HCMOS STRUCTURED ARRAY |
| ISB35484 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:HCMOS STRUCTURED ARRAY |
| ISB35666 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:HCMOS STRUCTURED ARRAY |
| ISB35832 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:HCMOS STRUCTURED ARRAY |
| ISB40 | 制造商:ISOCOM 制造商全称:ISOCOM 功能描述:Telecommunications |
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