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参数资料
| 型号： | IS82C50A-5 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | CMOS Asynchronous Communications Element |
| 中文描述： | 1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, MS-018AC, LCC-44 |
| 文件页数： | 7/21页 |
| 文件大小： | 101K |
| 代理商： | IS82C50A-5 |
7
LINE CONTROL REGISTER (LCR)
The format of the data character is controlled by the Line
Control Register. The contents of the LCR may be read,
eliminating the need for separate storage of the line charac-
teristics in system memory. The contents of the LCR are
described below.
LCR Bits 0 thru 7
LCR (0) Word Length Select Bit 0 (WLS0)
LCR (1) Word Length Select Bit 1 (WLS1)
LCR (2) Stop Bit Select (STB)
LOR (3) Parity Enable (PEN)
LCR (4) Even Parity Select (EPS)
LOR (5) Stick Parity
LOR (6) Set Break
LCR (7) Divisor Latch Access Bit (DLAB)
LCR(0) and LCR(1) Word Length Select Bit 0, Word
Length Select Bit 1:
The number of bits in each transmitted
or received serial character is programmed as follows:
LCR(2) Stop Bit Select:
LCR(2) specifies the number of
stop bits in each transmitted character. If LCR(2) is a logic 0,
one stop bit is generated in the transmitted data. If LCR(2) is
a logic 1 when a 5-bit word length is selected, 1.5 stop bits
are generated. If LCR(2) is a logic 1 when either a 6-, 7-, or
8-bit word length is selected, two stop bits are generated.
The receiver checks for two stop bits if programmed.
LCR(3) Parity Enable:
When LCR(3) is high, a parity bit
between the last data word bit and stop bit is generated and
checked.
LCR(4) Even Parity Select:
When parity is enabled
(LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1
selects even parity.
LCR(5) Stick Parity:
When parity is enabled (LCR(3) = 1),
LCR(5) = 1 causes the transmission and reception of a parity
bit to be in the opposite state from that indicated by LCR(4).
This allows the user to force parity to a known state and for
the receiver to check the parity bit in a known state.
LCR(6) Break Control:
When LCR(6) is set to logic-1, the
serial output (SOUT) is forced to the spacing (logic 0) state.
The break is disabled by setting LCR(6) to a logic-0. The
Break Control bit acts only on SOUT and has no effect on
the transmitter logic. Break Control enables the CPU to alert
a terminal in a computer communications system. If the
following sequence is used, no erroneous or extraneous
characters will be transmitted because of the break.
1. Load an all Os pad character in response to THRE.
2. Set break in response to the next THRE.
3. Wait for the transmitter to be idle, (TEMT = 1), and clear
break when normal transmission has to be restored.
During the break, the transmitter can be used as a character
timer to accurately establish the break duration.
LCR(7) Divisor Latch Access Bit (DLAB):
LCR(7) must
be set high (logic 1) to access the Divisor Latches DLL and
DLM of the Baud Rate Generator during a read or write
operation. LCR(7) must be input low to access the Receiver
Buffer, the Transmitter Holding Register, or the Interrupt
Enable Register.
LINE STATUS REGISTER (LSR)
The LSR is a single register that provides status indications.
The LSR is usually the first register read by the CPU to
determine the cause of an interrupt or to poll the status of
the 82C50A.
Three error flags OE, FE, and PE provide the status of any
error conditions detected in the receiver circuitry. During
reception of the stop bits, the error flags are set high by an
error condition. The error flags are not reset by the absence
of an error condition in the next received character. The flags
reflect the last character only if no overrun occurred. The
Overrun Error (OE) indicates that a character in the Receiver
Buffer Register has been overwritten by a character from the
Receiver Shift Register before being read by the CPU. The
character is lost. Framing Error (FE) indicates that the last
character received contained incorrect (low) stop bits. This is
caused by the absence of the required stop bit or by a stop
bit too short to be detected. Parity Error (PE) indicates that
the last character received contained a parity error based on
the programmed and calculated parity of the received
character.
The Break Interrupt (BI) status bit indicates that the last
character received was a break character. A break character
is an invalid data character, with the entire character,
including parity and stop bits, logic zero.
The Transmitter Holding Register Empty (THRE) bit
indicates that the THR register is empty and ready to receive
another character. The Transmission Shift Register Empty
(TEMT) bit indicates that the Transmitter Shift Register is
empty, and the 82C50A has completed transmission of the
last character. If the interrupt is enabled (lER(1)), an active
THRE causes an interrupt (INTRPT).
The Data Ready (DR) bit indicates that the RBR has been
loaded with a received character (including Break) and that
the CPU may access this data.
Reading the LSR clears LSR (1) - LSR (4). (OE, PE, FE and
BI).
LCR(1)
LCR(0)
WORD LENGTH
0
0
5 Bits
0
1
6 Bits
1
0
7 Bits
1
1
8 Bits
82C50A
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| IS82C50A-5Z | 功能描述:UART 接口集成电路 W/ANNEAL PERIPH UART /BRG 5V 10MHZ RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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