参数资料
| 型号： | ISL12024IRTCZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDER 64BIT 8-TDFN |
| 标准包装： | 6,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，唯一 ID |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TDFN |
| 供应商设备封装： | 8-TDFN（3x3） |
| 包装： | 带卷 (TR) |
19
FN6749.1
December 15, 2011
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
RANDOM READ
Random read operations allow the master to access any
location in the ISL12024IRTCZ. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master must
first perform a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8 -bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. See Figure 21 for the address,
acknowledge and data transfer sequence.
In a similar operation called “Set Current Address,” the device
sets the address if a stop is issued instead of the second start
shown in Figure 21. The ISL12024IRTCZ then goes into
Standby Power Mode after the stop and all bus activity will be
ignored until a start is detected. This operation loads the new
address into the address counter. The next Current Address
Read operation will read from the newly loaded address. This
operation could be useful if the master knows the next
address it needs to read, but is not ready for the data.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space the counter “rolls over” to the start of the
address space and the ISL12024IRTCZ continues to output
data for each acknowledge received. See Figure 22 for the
acknowledge and data transfer sequence.
ACK
RETURNED?
ISSUE MEMORY ARRAY SLAVE
ADDRESS BYTE
AFH (READ) OR AEH (WRITE)
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
ISSUE STOP
ISSUE START
NO
YES
ISSUE STOP
NO
CONTINUE
NORMAL READ OR
WRITE COMMAND
SEQUENCE
PROCEED
YES
NON-VOLATILE WRITE
CYCLE COMPLETE. CONTINUE
COMMAND SEQUENCE?
FIGURE 20. ACKNOWLEDGE POLLING SEQUENCE
0
SLAVE
ADDRESS
WORD
ADDRESS 1
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
DATA
A
C
K
1
S
T
A
R
T
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
A
C
K
WORD
ADDRESS 0
1
11
00 0 0 0 0 0
FIGURE 21. RANDOM ADDRESS READ SEQUENCE
ISL12024IRTC
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