参数资料
| 型号： | ISL12024IRTCZ |
| 厂商： | Intersil |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDER 64BIT 8-TDFN |
| 标准包装： | 100 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，唯一 ID |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TDFN |
| 供应商设备封装： | 8-TDFN（3x3） |
| 包装： | 管件 |
22
FN6749.1
December 15, 2011
to 10 years. Another option is to use a super capacitor for
applications where VDD may disappear intermittently for short
periods of time. Depending on the value of superconductor
used, backup time can last from a few days to two weeks (with
>1F). A simple silicon or Schottky barrier diode can be used in
series with VDD to charge the superconductor, which is
connected to the VBAT pin. Try to use Schottky diodes with
very low leakages, <1A desirable. Do not use the diode to
charge a battery (especially lithium batteries!)
There are two possible modes for battery backup operation;
Standard and Legacy Mode. In Standard Mode, there are no
operational concerns when switching over to battery backup
since all other devices functions are disabled. Battery drain
is minimal in Standard Mode, and return to Normal VDD
powered operations is predictable. In Legacy Mode, the
VBAT pin can power the chip if the voltage is above VDD and
less than VTRIP. In this mode, it is possible to generate alarm
and communicate with the device, unless SBI = 1, but the
supply current drain is much higher than the Standard Mode
and backup time is reduced. In this case if alarms are used
in backup mode, the IRQ/FOUT pull-up resistor must be
connected to VBAT voltage source. During initial power-up
the default mode is the Standard Mode.
Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
B. Also, the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/FOUT output
low.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
Once the registers are set, the following waveform will be
seen at IRQ/FOUT:
ALARM0
REGISTER
BIT
DESCRIPTION
76
543210
HEX
SCA0
00
000000
00h
Seconds disabled
MNA0
10
110000
B0h Minutes set to 30,
enabled
HRA0
1
0
010001
91h
Hours set to 11,
enabled
DTA0
10
000001
81h
Date set to 1,
enabled
MOA0
10
000001
81h
Month set to 1,
enabled
FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT
VDD
VBAT
VSS
SUPER CAPACITOR
2.7V TO 5.5V
DWA0
0
0000000
00h
Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
765
43210
HEX
INT
001
00000
x0hEnable Alarm
ALARM0
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA0
10110000 B0h Seconds set to 30,
enabled
MNA0
00000000 00h Minutes disabled
HRA0
00000000 00h Hours disabled
DTA0
00000000 00h Date disabled
MOA0
00000000 00h Month disabled
DWA0
00000000 00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
76543210 HEX
INT
10100000
x0hEnable Alarm and Int
Mode
ALARM0
REGISTER
BIT
DESCRIPTION
7
6543210
HEX
60s
RTC AND ALARM REGISTERS ARE BOTH 30s
FIGURE 25.
ISL12024IRTC
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