参数资料
| 型号： | ISL12026IBZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8SOIC |
| 标准包装： | 250 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年 |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
14
FN8231.9
November 30, 2010
The ISL12026 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
- Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS ≈ 50mV
- Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS ≈ 30mV
There are two discrete situations that are possible when
using Standard Mode: VBAT < VTRIP and VBAT > VTRIP.
These two power control situations are illustrated in Figures
OPTION 2 -LEGACY POWER CONTROL MODE
(ISL12026 DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from VDD to VBAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the VBAT voltage is
higher than VDD, then the device will enter battery back up
and unless the battery is disconnected or the voltage
decreases, the device will no longer operate from VDD.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”
Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, the following
conditions must be met:
VDD < VBAT - VBATHYS
Battery Backup Mode (VBAT) to Normal Mode (VDD)
The device will switch from the VBAT to VDD mode when the
following condition occurs:
VDD > VBAT +VBATHYS
The Legacy Mode power control conditions are illustrated in
Figure 11.
Serial Communication
The device supports the I2C protocol.
Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 12).
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 13).
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus (see Figure 13).
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8 bits of data
(see Figure 14).
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will not acknowledge if the slave
address byte is incorrect.
BATTERY BACKUP
MODE
VDD
2.2V
FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VBAT
VTRIP
1.8V
VBAT + VBATHYS
VBAT - VBATHYS
FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP
VTRIP
VBAT
VTRIP + VTRIPHYS
BATTERY BACKUP
MODE
VDD
VTRIP
3.0V
2.2V
VBAT
In
VOLTAGE
VDD
ON
Off
FIGURE 11. BATTERY SWITCHOVER IN LEGACY MODE
ISL12026, ISL12026A
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