参数资料
| 型号： | ISL12032IVZ |
| 厂商： | Intersil |
| 文件页数： | 6/26页 |
| 文件大小： | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 14TSSOP |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 960 |
| 类型： | 时间事件记录器 |
| 特点： | 警报器，SRAM，涓流充电器 |
| 存储容量： | 128B |
| 时间格式： | HH:MM:SS:hh（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 管件 |
14
FN6618.3
May 5, 2011
BATTERY ACTIVE MODE (BMODE)
BMODE Indicates that the device is operating from the VBAT
input. A “1” indicates Battery Mode and a “0” indicates power
from VDD mode. The I2CBAT bit must be set to “1” and the
device must be in VBAT mode in order for a valid “1” read
from this bit.
DAYLIGHT SAVING TIME ADJUSTMENT BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjustment Bit. It
indicates that daylight saving time adjustment has
happened. The bit will be set to “1” when the Forward DST
event has occurred. The bit will stay set until the Reverse
DST event has happened. The bit will also reset to “0” when
the DSTE bit is set to “0” (DST function disabled). The bit
can be forced to “1” with by writing “F0h” to the Status
Register. The default value for DSTADJ is “0”.
ALARM BITS (ALM0 AND ALM1)
These bits announce if an alarm matches the real time clock.
If there is a match, the respective bit is set to “1”. This bit can
be manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in
the SR can only set it to “0”, not “1”. An alarm bit that is set by
an alarm occurring during an SR read operation will remain
set after the read operation is complete.
LOW VDD INDICATOR BIT (LVDD)
Indicates VDD dropped below the pre-selected trip level.
(Brownout Mode). The Trip points for Brownout levels are
selected by three bits VDDTrip2, VDDTrip1 and VDDTrip0 in
the PWRVDD registers.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
Indicates battery level dropped below the pre-selected trip
level (85% of battery voltage). The trip point is set by three
bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the PWRBAT
register.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
Indicates battery level dropped below the pre-selected trip
level (75% of battery voltage). The trip point is set by three
bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the PWRBAT
register.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (internally) when the device
powers up after having lost all power (defined as VDD = 0V
and VBAT = 0V). The bit is set regardless of whether VDD or
VBAT is applied first. The loss of only one of the supplies
does not set the RTCF bit to “1”. The first valid write to the
RTC section after a complete power failure resets the RTCF
bit to “0” (writing one byte is sufficient).
Status Register (SRAC)
The Status Register AC is located in the memory map at
address 09h. This is a volatile register that provides status of
Crystal Failure (XOSCF), AC Failed (ACFAIL) and AC
Ready (ACRDY).
CRYSTAL OSCILLATOR FAIL BIT (XOSCF)
Indicates Crystal Oscillator has stopped if XOSCF = 1. When
the crystal oscillator has resumed operation, the XOSCF bit
is reset to “0”.
AC FAIL (ACFAIL)
This bit announces the status of the AC input. If ACFAIL = 1,
then the AC input frequency and amplitude qualification
check has failed. ACFAIL is reset to “0” when the AC input
meets the preset requirements (see “AC (AC Input)” on
page 8).
AC READY (ACRDY)
This bit announces the status of the AC input. If ACRDY = 1,
then the AC input has passed the qualification parameter
check (as set by ACFC and ACFP bits) for the time
prescribed by ACRP and is used for the RTC clock. When
ACRDY = 0 the AC input failed the qualification
requirements and the crystal oscillator clock is used for the
RTC clock (see “AC (AC Input)” on page 8).
When ACFAIL transitions from “1” to “0” (from failed to pass),
then the timer set by ACRP will determine the delay until
ACRDY transitions from “0” to “1”. ACRDY will be set to “0”
immediately after ACRDY is set to “0” (failed AC input),
indicating the crystal oscillator is the RTC clock.
Counter Registers
Addresses [0Ah to 0Bh]
These registers will count the number of times AC failure
occurs and the number of times an event occurs. These
registers are 8-bits each and will count up to 255.
AC COUNT (ACCNT)
The ACCNT register increments automatically each time the
AC input switches to the crystal backup. The register is set to
00h on initial power-up. The maximum count is 255, and will
stay at that value until set to zero via an I2C write.
TABLE 2. STATUS REGISTER DC (SRDC)
ADDR
7
6
5
4
3
2
1
0
08h
BMODE DSTADJ ALM1
ALM0 LVDD LBAT85 LBAT75 RTCF
TABLE 3. STATUS REGISTER AC (SRAC)
ADDR
7
6
5
4
3
2
1
0
09h
X
XOSCF
X
ACFAIL
ACRDY
TABLE 4. AC COUNTER REGISTER (ACCNT)
ADDR
7
6
5
4
3
2
1
0
0Ah
AXC7
AXC6
AXC5
AXC4
AXC3
AXC2
AXC1
AXC0
ISL12032
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