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参数资料
| 型号： | ISL22329 |
| 厂商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power, I2C Bus, 128 Taps, Wiper Only(低噪声,低功率，I2C总线, 128抽头电位器) |
| 中文描述： | 低噪声，低功耗，I2C总线，128抽头，雨刷，只有（低噪声，低功率和I2C总线，128抽头电位器） |
| 文件页数： | 9/12页 |
| 文件大小： | 333K |
| 代理商： | ISL22329 |
9
FN6330.1
September 26, 2006
Bus Interface Pins
Serial Data Input/Output (SDA)
The SDA is a bidirectional serial data input/output pin for I
2
C
interface. It receives device address, operation code, wiper
address and data from an I
2
C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
Serial Clock (SCL)
This is the serial clock input of the I
2
C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
Device Address (A2 - A0)
The address inputs are used to set the least significant 3 bits
of the 7-bit I
2
C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22329. A maximum of 8 ISL22329 devices may occupy
the I
2
C serial bus.
Principles of Operation
The ISL22329 is an integrated circuit incorporating two
DCPs with their associated registers, non-volatile memory
and an I
2
C serial interface providing direct communication
between a host and the potentiometers and memory. The
resistor arrays are comprised of individual resistors
connected in series. At either end of the array and between
each resistor is an electronic switch that transfers the
potential at that point to the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
loaded into the corresponding WRi to set the wipers to the
initial value.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to Vcc and GND.
The RW pin of each DCP is connected to intermediate
nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by volatile Wiper Register (WR).
Each DCP has its own WR. When the WR of a DCP contains
all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest
to GND. When the WR register of a DCP contains all ones
(WR[6:0]= 7Fh), its wiper terminal (RW) is closest to V
CC
. As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to GND to the closest to V
CC
.
While the ISL22329 is being powered up, all WRs are reset
to 40h (64 decimal), which locates RW roughly at the center
between GND and V
CC
. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).
The WRs can be read or written to directly using the I
2
C
serial interface as described in the following sections. The
I
2
C interface Address Byte has to be set to 00h or 01h to
access the WR of DCP0 or DCP1 respectively.
Memory Description
The ISL22329 contains seven non-volatile and three volatile
8-bit registers. The memory map of ISL22329 is on Table 1.
The two non-volatile registers (IVRi) at address 0 and 1,
contain initial wiper value and volatile registers (WRi) contain
current wiper position. In addition, five non-volatile General
Purpose registers from address 2 to address 6 are available.
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information and
control bits described below in Table 2. The VOL bit at access
control register (ACR[7]) determines whether the access is to
wiper registers WRi or initial value registers IVRi.
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible. Note,
value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically OR’d with SHDN pin. When this bit
is 0, DCPs are in Shutdown mode. Default value of SHDN bit
is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the IVRi, WRi or ACR while WIP bit is 1.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
—
ACR
7
Reserved
6
5
4
3
2
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
Not Available
Not Available
Not Available
Not Available
Not Available
1
0
IVR1
IVR0
WR1
WR0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN
WIP
0
0
0
0
0
ISL22329
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