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| 型号： | ISL22349 |
| 厂商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power, I2C Bus, 128 Taps, Wiper Only(低噪声,低功率，I2C总线, 128抽头电位器) |
| 中文描述： | 低噪声，低功耗，I2C总线，128抽头，雨刷，只有（低噪声，低功率和I2C总线，128抽头电位器） |
| 文件页数： | 10/12页 |
| 文件大小： | 332K |
| 代理商： | ISL22349 |
10
FN6331.2
September 15, 2006
The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WRi or ACR while WIP bit is 1.
I
2
C Serial Interface
The ISL22349 supports an I
2
C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22349
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 12). On power-up of the ISL22349 the SDA pin is in
the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22349 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met. A
START condition is ignored during the power-up of the
device.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 12). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL22349 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22349 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 1010b as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (See Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
1
0
1
0
A2
A1
A0
R/W
(MSB)
(LSB)
Logic values at pins A2, A1, and A0 respectively
SDA
SCL
START
DATA
STABLE
DATA
CHANGE
STOP
DATA
STABLE
FIGURE 12. VALID DATA CHANGES, START AND STOP CONDITIONS
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
ISL22349
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