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参数资料
| 型号： | ISL23711WIU10Z |
| 厂商： | INTERSIL CORP |
| 元件分类： | 数字电位计 |
| 英文描述： | Terminal Voltage +-3V or +-5V, 128 Taps IC Serial Interface |
| 中文描述： | 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO10 |
| 封装： | ROHS COMPLIANT, PLASTIC, MO-187BA, MSOP-10 |
| 文件页数： | 4/9页 |
| 文件大小： | 270K |
| 代理商： | ISL23711WIU10Z |
4
FN6127.0
August 16, 2005
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
I
CC1
V
CC
Supply Current, Volatile
Write/Read
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Write states only)
200
μ
A
I
V-
V- Supply Current, Volatile Write/Read f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Write states only)
-100
-1
μ
A
I
SB
V
CC
Current (Standby)
V
CC
= +5.5V, I
2
C Interface in Standby State
V
CC
= +3.6V, I
2
C Interface in Standby State
V-
= -5.5V, I
2
C Interface in Standby State
V-
= -2.7V, I
2
C Interface in Standby State
500
nA
300
nA
I
V-SB
V- Current (Standby)
-500
nA
-300
-1
nA
I
LkgDig
Leakage Current, at Pins SDA, SCL,
A0, and A1
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 13)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1
μs
Vpor
Power-on Recall for V
CC
2.5
V
SERIAL INTERFACE SPECS
V
IL
A0, A1, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*V
CC
V
V
IH
A0, A1, SDA, and SCL Input Buffer
HIGH Voltage
0.7*V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
V
CC
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0
0.4
V
Cpin
(Note 14)
A0, A1, SDA, and SCL Pin
Capacitance
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window
900
ns
t
BUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
CC
crossing
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
CC
crossing
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
100
ns
t
HD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
600
ns
t
HD:STO
STOP Condition Setup Time
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
600
ns
ISL23711
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