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参数资料
| 型号： | ISL23711WIU10Z |
| 厂商： | INTERSIL CORP |
| 元件分类： | 数字电位计 |
| 英文描述： | Terminal Voltage +-3V or +-5V, 128 Taps IC Serial Interface |
| 中文描述： | 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO10 |
| 封装： | ROHS COMPLIANT, PLASTIC, MO-187BA, MSOP-10 |
| 文件页数： | 5/9页 |
| 文件大小： | 270K |
| 代理商： | ISL23711WIU10Z |
5
FN6127.0
August 16, 2005
SDA vs SCL Timing
A0, A1 Pin Timing
t
DH
Output Data Hold Time
From SCL falling edge crossing 30% of V
CC
, until
SDA enters the 30% to 70% of V
CC
window
0
ns
t
R
(Note 14)
SDA, SCL, A0, A1 Rise Time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
(Note 14)
SDA, SCL, A0, A1 Fall Time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
(Note 14)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 14)
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
k
t
SU:A
A0, A1 Setup Time
Before START condition
600
ns
t
HD:A
A0, A1 Hold Time
After STOP condition
600
ns
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:A
SCL
SDA IN
A0, A1
t
SU:A
Clk 1
START
STOP
ISL23711
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