参数资料
型号: ISL26132AVZ
厂商: Intersil
文件页数: 6/23页
文件大小: 0K
描述: IC ADC 24BIT SRL 80SPS 24TSSOP
标准包装: 620
位数: 24
采样率(每秒): 80
数据接口: 串行
转换器数目: 1
功率耗散(最大): 80mW
电压电源: 模拟和数字
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
输入数目和类型: 2 个差分,双极
ISL26132, ISL26134
14
FN6954.1
September 9, 2011
Serial Clock Input (SCLK)
The serial clock input is provided with hysteresis to minimize
false triggering. Nevertheless, care should be taken to ensure
reliable clocking.
Filter Settling Time and ADC Latency
Whenever the analog signal into the ISL26132, ISL26134
converters is changed, the effects of the digital filter must be
taken into account. The filter takes four data ready periods for
the output code to fully reflect a new value at the analog input. If
the multiplexer control input is changed, the modulator and the
digital filter are reset, and the device uses four data ready
periods to fully settle to yield a digital code that accurately
represents the analog input. Therefore, from the time the control
inputs for the multiplexer are changed until the SDO/RDY goes
low, four data ready periods will elapse. The settling time delay
after a multiplexer channel change is listed in Table 8 for the
converter operating in continuous conversion mode.
0
-50
-100
-150
0
1020
30
40
50607080
90 100
FREQUENCY (Hz)
GAIN
(dB)
DATA RATE = 10 SPS
DATA RATE = 10Sps
FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
45
50
55
60
65
FREQUENCY (Hz)
GAIN
(dB)
DATA RATE = 10Sps
FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz
TABLE 8. SETTLING TIME
PARAMETER
DESCRIPTION
(fCLK = 4.9152MHz)
MIN
MAX
UNITS
tS
A0, A1, SPEED, Gain1, Gain0 change
set-up time
40
50
s
t1
Settling time
SPEED = 1
54
55
ms
SPEED = 0
404
405
ms
FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
tS
t1
A0, A1, SPEED, Gain1, Gain0
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