参数资料
| 型号： | ISL26132AVZ |
| 厂商： | Intersil |
| 文件页数： | 7/23页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SRL 80SPS 24TSSOP |
| 标准包装： | 620 |
| 位数： | 24 |
| 采样率（每秒）： | 80 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 80mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，双极 |
ISL26132, ISL26134
15
FN6954.1
September 9, 2011
Conversion Data Rate
The SPEED pin is used to select between the 10Sps and 80Sps
conversion rates. The 10Sps rate (SPEED = Low) is preferred in
applications requiring 50/60Hz noise rejection. Note that the
sample rate is directly related to the oscillator frequency, as
491,520 clocks are required to perform a conversion at the
10Sps rate, and 61,440 clocks at the 80Sps rate.
Output Data Format
The 24-bit converter output word is delivered in two’s
complement format. Input exceeding full scale results in a
clipped output which will not return to in-range values until after
the input signal has returned to the specified allowable voltage
range and the digital filter has settled as discussed previously.
Reading Conversion Data from the Serial
Data Output/Ready SDO/RDY Pin
When the ADC is powered, it will automatically begin doing
conversions. The SDO/RDY signal will go low to indicate the
completion of a conversion. After the SDO/RDY signal goes low,
the MSB data bit of the conversion word will be output from the
SDO/RDY pin after SCLK is transitioned from a low to a high.
Each subsequent new data bit is also output on the rising edge of
SCLK (see Figure 30). The receiving device should use the falling
edge of SCLK to latch the data bits. After the 24th SCLK, the
SDO/RDY output will remain in the state of the LSB data bit until
a new conversion is completed. At this time, the SDO/RDY will go
high if low and then go low to indicate that a new conversion
word is available. If not all data bits are read from the SDO/RDY
pin prior to the completion of a new conversion, they will be
overwritten. SCLK should be low during time t6, as shown in
Figure 30, when SDO/RDY is high.
If the user wants the SDO/RDY signal to go high after reading the
24 bits of the conversion data word, a 25th SCLK can be issued.
The 25th SCLK will force the SDO/RDY signal to go high and
remain high until it falls to signal that a new conversion word is
available. Figure 31 illustrates the behavior of the SDO/RDY
signal when a 25th SCLK is used.
FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT
INPUT SIGNAL
OUTPUT CODE (HEX)
≥ + 0.5VREF/GAIN
7FFFFF
(+0.5VREF/GAIN)/(223 - 1)
000001
0
000000
(-0.5VREF/GAIN)/(223 - 1)
FFFFFF
≤ - 0.5VREF/GAIN
800000
FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA
SDO/RDY
DATA READY
DATA
MSB
LSB
NEW DATA READY
23
22
21
0
SCLK
t4
t2
1
t3
24
t5
t6
t3
t7
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL26132AVZ-T | 功能描述:模数转换器 - ADC ISL26132AVZ LW-NOISE 24-BIT TI-COMP D/S RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ISL26132AVZ-T7A | 功能描述:模数转换器 - ADC ISL26132AVZ LW-NOISE 24BIT DELTASIGMA ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ISL26134 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Low-Noise 24-bit Delta Sigma ADC |
| ISL26134AV28EV1Z | 功能描述:数据转换 IC 开发工具 ISL26134 EVALRD 1 2 8LD ROHS CMPL RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| ISL26134AVZ | 功能描述:模数转换器 - ADC ISL26134AVZ LW-NOISE 24-BIT TI-COMP D/S RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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