参数资料
| 型号： | ISL2671286IBZ |
| 厂商： | Intersil |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SPI/SRL 20K 8SOIC |
| 标准包装： | 980 |
| 位数： | 12 |
| 采样率（每秒）： | 20k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.4mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极 |
ISL2671286
11
FN7863.0
November 1, 2011
Functional Description
The ISL2671286 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital-to-analog converters (DACs). Figure 26 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage can be converted to digital
format. The comparator becomes unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one-quarter of full-scale by switching in binarily weighted
capacitors. Again, the comparator output reflects whether the
stored voltage is above or below the new value and sets the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
ADC Transfer Function
The output coding for the ISL2671286 is straight binary. The first
code transition occurs at successive LSB values (i.e., 1 LSB, 2
LSB, and so on). The LSB size is VREF/4096. The ideal transfer
characteristic of the ISL2671286 is shown in Figure 27.
Analog Input
The ISL2671286 features a pseudo-differential input with a
nominal full-scale range equal to the applied VREF voltage. The
negative input (VIN–) must be biased within 200mV of ground.
Modes of Operation
There are two possible modes of operation, which are controlled
by the CS/SHDN signal. When CS/SHDN is high (deasserted), the
ADC is in static mode. Conversely, when CS/SHDN is low
(asserted), the device is in dynamic mode. There is no minimum
or maximum number of SCLK cycles required to enter static
mode. This simplifies power management and allows the user to
easily optimize power dissipation versus throughput for various
application requirements.
DYNAMIC MODE
This mode is entered when a conversion result is desired by
asserting CS/SHDN. Figure 28 shows the general operation in
this mode. The conversion is initiated on the falling edge of
CS/SHDN (refer to “Serial Digital Interface” section). When
CS/SHDN is deasserted, the conversion is terminated, and DOUT
returns to a high-impedance state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
conversion result. CS/SHDN may idle high until the next
conversion or idle low until sometime prior to the next
conversion. Once a data transfer is complete (DOUT has returned
to a high-impedance state), another conversion can be initiated
by again asserting CS/SHDN.
STANDBY MODE
The ISL2671286 enters the power-saving static mode
automatically any time CS/SHDN is deasserted. The user is not
required to force a device into this mode following a conversion
in order to optimize power consumption.
SHORT CYCLING
In cases where a lower resolution conversion is acceptable,
CS/SHDN can be pulled high before 12 SCLK falling edges have
elapsed. This is referred to as short cycling, and it can be used to
further optimize power dissipation. In this mode, a lower
resolution result is acquired, but the ADC enters static mode
sooner and exhibits a lower average power dissipation than if the
complete conversion cycle is carried out. The acquisition time
(tACQ) requirement must be met for the next conversion to be
valid.
POWER-ON RESET
The ISL2671286 performs a power-on reset that requires
approximately 2.5ms to execute when the supplies are first
FIGURE 26. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
VIN+
VIN–
VREF
ACQ
CONV
ACQ
CONV
DAC
DA
C
SAR
LOGIC
1LSB = VREF/4096
000...000
000...001
000...010
011...111
100...000
100...001
111...110
111...111
AD
C
CO
DE
ANALOG INPUT
+IN –(–IN)
+LSB
+VREF
– 1LSB
0V
+VREF
– 1LSB
FIGURE 27. IDEAL TRANSFER CHARACTERISTICS
SCLK
DOUT
CSB
10
116
4 LEADING ZEROS AND CONVERSION RESULT
FIGURE 28. NORMAL MODE OPERATION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL2671286IBZ-T | 功能描述:模数转换器 - ADC 12 BIT SINGLE ENDED 20KHZ SAR ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ISL2671286IBZ-T7A | 功能描述:模数转换器 - ADC 12 BIT SNG ENDED 20K HZ SAR ADC 8LD RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ISL26712IHZ-T | 制造商:Intersil Corporation 功能描述:12 BIT 1MSPS SAR ADC IN 8 LEAD SOT-23, T&R (PROPRIETARY) - Tape and Reel 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 1M 8SOT-23 制造商:Intersil 功能描述:12 Bit 1MSPS SAR ADC in 8 Lead SOT-23, T |
| ISL26712IHZ-T7A | 制造商:Intersil Corporation 功能描述:12 BIT 1MSPS SAR ADC IN 8 LEAD SOT-23, 250PC T&R (PROPRIETAR - Tape and Reel 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 1M 8SOT-23 制造商:Intersil 功能描述:12 Bit 1MSPS SAR ADC in 8 Lead SOT-23, 2 |
| ISL26712IRTZ | 功能描述:IC ADC 12BIT SAR 1MSPS 8-TDFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
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