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参数资料
| 型号： | ISL29003IROZ-EVALZ |
| 厂商： | Intersil |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL29003 |
| 标准包装： | 1 |
| 传感器类型： | 灯光，数字式输出 |
| 传感范围： | 64000Lux |
| 接口： | I²C |
| 灵敏度： | 550nm |
| 电源电压： | 2.25 V ~ 3.3 V |
| 嵌入式： | 否 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL29003 |
ISL29003
TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES
TABLE 11. DATA REGISTERS
FSR LUX
FSR LUX
FSR LUX
ADDRESS
BITS
RANGE@
RANGE@
RANGE@
(hex)
CONTENTS
3:2 k RANGE (k) R EXT = 100k R EXT = 50k R EXT = 500k
04
Least-significant byte of most recent sensor reading.
0:0
0:1
1:0
1:1
1
2
3
4
973
3892
15,568
62,272
973
3892
15,568
62,272
1946
7784
31,136
124,544
195
778
3114
12,454
05
06
07
Most-significant byte of most recent sensor reading.
Least-significant byte of timer counter value
corresponding to most recent sensor reading.
Most-significant byte of timer counter value
corresponding to most recent sensor reading.
3. Interrupt persist; Bits 1 and 0. The interrupt pin and the
interrupt flag is triggered/set when the data sensor
reading is out of the interrupt threshold window after m
consecutive number of integration cycles. The interrupt
Calculating Lux
The ISL29003’s output codes, DATA, are directly
proportional to lux.
persist bits determine m.
E = α × DATA
(EQ. 1)
TABLE 10. INTERRUPT PERSIST
BITS 1:0 NUMBER OF INTEGRATION CYCLES
The proportionality constant α is determined by the Full
Scale Range, FSR, and the n-bit ADC, which is user defined
0:0
1
in the command register. The proportionality constant can
α = ------------
0:1
1:0
1:1
4
8
16
also be viewed as the resolution; The smallest lux
measurement the device can measure is α .
FSR
n
2
(EQ. 2)
FSR = Range ( k ) × ------------------
Interrupt Threshold HI Register 02(hex)
This register sets the HI threshold for the interrupt pin and
the interrupt flag. By default, the Interrupt threshold HI is
FF(hex). The 8-bit data written to the register represents the
upper MSB of a 16-bit value. The LSB is always 00(hex).
Interrupt Threshold LO Register 03(hex)
This register sets the LO threshold for the interrupt pin and
the interrupt flag. By default, the Interrupt threshold LO is
00(hex). The 8-bit data written to the register represents the
Full Scale Range, FSR, is determined by the software
programmable Range/Gain, Range(k), in the command
register and an external scaling resistor R EXT which is
referenced to 100k Ω .
100k Ω (EQ. 3)
R EXT
The transfer function effectively for each timing mode
becomes:
INTERNAL TIMING MODE
Range ( k ) × ------------------
R EXT
Range ( k ) × ------------------
R EXT
upper MSB of a 16-bit value. The LSB is always 00(hex).
Sensor Data Register 04(hex) and 05(hex)
When the device is configured to output a 16-bit data, the
least significant byte is accessed at 04(hex), and the most
significant byte can be accessed at 05(hex). The sensor data
register is refreshed after every integration cycle.
Timer Data Register 06(hex) and 07(hex)
Note that the timer counter value is only available when
using the External Timing Mode. The 06(hex) and 07(hex)
100k Ω
E = ---------------------------------------------------- × DATA
n
2
EXTERNAL TIMING MODE
100k Ω
E = ---------------------------------------------------- × DATA
COUNTER
n = 4, 8, 12, or 16. This is the number of clock cycles
programmed in the command register.
(EQ. 4)
(EQ. 5)
are the LSB and MSB respectively of a 16-bit timer counter
value corresponding to the most recent sensor reading.
Each clock cycle increments the counter. At the end of each
integration period, the value of this counter is made available
over the I 2 C. This value can be used to eliminate noise
introduced by slight timing errors caused by imprecise
external timing. Microcontrollers, for example, often cannot
provide high-accuracy command-to-command timing, and
the timer counter value can be used to eliminate the
resulting noise.
7
Range(k) is the user defined range in the Gain/Range bit in
the command register.
R EXT is an external scaling resistor hardwired to the R EXT
pin.
DATA is the output sensor reading in number of counts
available at the data register.
2 n represents the maximum number of counts possible in
Internal Timing Mode. For the External Timing Mode, the
maximum number of counts is stored in the data register
named COUNTER.
FN7464.6
November 17, 2011
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