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参数资料
| 型号： | ISL29023IROZ-EVALZ |
| 厂商： | Intersil |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD ISL29023IROZ |
| 标准包装： | 1 |
| 传感器类型： | 灯光，数字式输出 |
| 传感范围： | 64000Lux |
| 接口： | I²C，SM 总线 |
| 灵敏度： | 540nm |
| 电源电压： | 2.25 V ~ 3.63 V |
| 嵌入式： | 否 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL29023 |
ISL29023
TABLE 1. REGISTER MAP
Register Address
Register Bits
DEFAULT
NAME
DEC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
HEX
COMMAND-I
0
0x00
OP2
OP1
OP0
RESERVED
FLAG
PRST1
PRST0
0x00
COMMAND-II
1
0x01
RESERVED
RES1
RES0
RANGE1
RANGE0
0x00
DATA LSB
DATA MSB
INT_LT_LSB
INT_LT_MSB
INT_HT_LSB
INT_HT_MSB
2
3
4
5
6
7
0x02
0x03
0x04
0x05
0x06
0x07
D7
D15
TL7
TL15
TH7
TH15
D6
D14
TL6
TL14
TH6
TH14
D5
D13
TL5
TL13
TH5
TH13
D4
D12
TL4
TL12
TH4
TH12
D3
D11
TL3
TL11
TH3
TH11
D2
D10
TL2
TL10
TH2
TH10
D1
D9
TL1
TL9
TH1
TH9
D0
D8
TL0
TL8
TH0
TH8
0x00
0x00
0x00
0x00
0xFF
0xFF
Register Description
Following are detailed descriptions of the control registers
related to the operation of the ISL29023 ambient light sensor
device. These register are accessed by the I 2 C serial interface.
All the functionalities of the device are controlled by the
registers. The ADC data can also be read. The following sections
explain the details of each register bit. All RESERVED bits must
be set to zero, unless otherwise specified.
Decimal to Hexadecimal Conversion
To convert decimal value to hexadecimal value, divide the
decimal number by 16, and write the remainder on the side as
INTERRUPT PERSIST BITS (B0 - B1)
The interrupt persist bits provides control over when interrupts
occur. There are four different selections for this feature. A value
of N (where N is 1, 4, 8, and 16) results in an interrupt only if the
value remains outside the threshold window for N consecutive
integration cycles. For example, if N is equal to 16 and the ADC
resolution is set to 16-bits then the integration time is 100ms. An
interrupt is generated whenever the last conversion results in a
value outside of the programmed threshold window. The
interrupt is active-low and remains asserted until cleared by
writing the COMMAND register with the CLEAR bit set. Table 4
lists the possible interrupt presist bits.
TABLE 4. INTERRUPT PERSIST BITS
B1 B0 NUMBER OF INTEGRATION CYCLES (n)
the least significant digit. This process is continued by dividing
the quotient by 16 and writing the remainder until the quotient is
0. When performing the division, the remainders, which will
represent the hexadecimal equivalent of the decimal number,
are written beginning at the least significant digit (right) and
0
0
1
1
0
1
0
1
1
4
8
16
each new digit is written to the next more significant digit (the
left) of the previous digit. Consider the number 175 decimal.
INTERRUPT FLAG BIT (B2)
DIVISION
TABLE 2. DECIMAL TO HEXADECIMAL
QUOTIENT REMINDER
HEX NUMBER
The interrupt flag bit is a status bit for light intensity detection.
The bit is set to logic HIGH when the light intensity crosses the
interrupt thresholds window (register address 0x04 - 0x07), and
175/16
10 = A
15 = F
0xAF
set to logic LOW when its within the interrupt thresholds window.
Once the interrupt is triggered, the INT pin goes low and the
Command-I Register (Address: 0x00)
TABLE 3. COMMAND-I REGISTER ADDRESS
interrupt status bit goes HIGH until the status bit is polled
through the I 2 C read command. Both the INT pin and the
interrupt status bit are automatically cleared at the end of the
Reg. Addr
Register Bits
DFLT
8-bit Device Register byte (0x00) transfer. Table 5 shows interrupt
flag states.
NAME
COMMANDI
(Hex)
0x00
B7 B6 B5 B4 B3 B2 B1 B0 (Hex)
OP2 OP1 OP0 0 0 FLAG PRST1 PRST0 0x00
BIT 2
TABLE 5. INTERRUPT FLAG BIT
OPERATION
The Command-I register consists of control and status bits. In
this register, there are two interrupt persist bits, one interrupt
status bit, and three operation mode bits. The operation mode
bits and the interrupt persist bits are independent of each other.
The default register value is 0x00 at power on.
8
0
1
Interrupt is cleared or not triggered yet
Interrupt is triggered
FN6691.3
April 25, 2013
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