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参数资料
| 型号： | ISL45042IRZ-TK |
| 厂商： | INTERSIL CORP |
| 元件分类： | 消费家电 |
| 英文描述： | LCD Module Calibrator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO8 |
| 封装： | 3 X 3 MM, LEAD FREE, PLASTIC, TDFN-8 |
| 文件页数： | 4/8页 |
| 文件大小： | 129K |
| 代理商： | ISL45042IRZ-TK |
4
FN6072.6
November 14, 2006
Application Information
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042 has a 128-step
sink current resolution. The output is connected to an
external voltage divider, that results in decreasing the output
VCOM voltage as you increase the ISL45042 sink current.
CTL Pin
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL, when the CE pin is high.
The output VCOM voltage is increased with a mid (Vdd/2) to
high transition (0.8*VDD) on CTL pin. The output VCOM
voltage is decreased with a mid (Vdd/2) to low transition
(0.3*VDD), on CTL pin (Reference Figure 6). Once the
minimum or maximum value is reached on the 128 steps,
the device will not overflow or underflow beyond that
minimum or maximum value.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200μs. The level and timing
needed to program the non-volatile memory is given in
Figure 2. It then takes a maximum of 100ms for the
programming to be completed inside the device.
Programming Time
P
T
Full
100
ms
SET Voltage Resolution
SET
VR
(Note 4)
Full
7
7
7
Bits
SET Differential Nonlinearity
SET
DN
Monotonic Over Temperature
Full
-
-
±
1
LSB
SET Zero-Scale Error
SET
ZSE
Full
-
-
±
2
LSB
SET Full-Scale Error
SET
FSE
Full
-
-
±
8
LSB
SET Current
ISET
Through R
SET
(Note 7)
Full
-
20
-
μ
A
SET External Resistance
SET
ER
To GND, AVDD = 20V
Full
10
-
200
k
Ω
To GND, AVDD = 4.5V
Full
2.25
-
45
k
Ω
AVDD to SET Voltage Attenuation
AVDD to SET
Full
-
1:20
-
V/V
OUT Settling Time
OUT
ST
to
±
0.5 LSB Error Band (Note 5)
Full
-
20
-
μ
s
OUT Voltage Range
V
OUT
Full
VSET +
0.5V
-
13
V
OUT Voltage Drift
OUT
VD
(Note 5)
25 to 55
-
<10
-
mV
NOTES:
2. CTL signal only needs to be greater than 4.9V to program EEPROM.
3. Tested at AVDD = 20V.
4. The Counter value is set to mid-scale
±
4 LSB’s in the Production.
5. Simulated and Determined via Design and NOT Directly Tested.
6. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply.
7. A Typical Current of 20
μ
A is Calculated using the AVDD = 10V and RSET = 24.9k
Ω
. The maximum suggested SET Current should be 120
μ
A.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9k
Ω
; Unless Otherwise Specified.
Typicals are at T
A
= +25°C
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
R
SET
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
ISL45042
CTL
CE
SET
OUT
AVDD
R
1
R
2
AVDD
I
Sink
VCOM
SINGLE PIXEL
IN LCD PANEL
R
G
B
+
-
COLUMN
DRIVER
ISL45042
相关PDF资料 |
PDF描述 |
|---|---|
| ISL45042 | LCD Module Calibrator |
| ISL45042IR-T | LCD Module Calibrator |
| ISL45042IR | LCD Module Calibrator |
| ISL45042IRZ | LCD Module Calibrator |
| ISL45042IRZ-T | LCD Module Calibrator |
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