参数资料
型号: ISL54063EVAL1Z
厂商: Intersil
文件页数: 7/15页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL54063
标准包装: 1
主要目的: 接口,模拟开关
嵌入式:
已用 IC / 零件: ISL54063
主要属性: 2 x SPST 模拟开关
次要属性: 1.8 V ~ 6.5 V 电源
已供物品:
15
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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FN6582.1
November 3, 2009
ISL54063, ISL54064
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 C
A
0.10 C
A1
SEATING PLANE
INDEX AREA
2
1
N
TOP VIEW
SIDE VIEW
NX (b)
SECTION "C-C"
e
CC
5
C
L
TERMINAL TIP
(A1)
L
0.10 C
2X
L1
e
NX L
BOTTOM VIEW
5
7
2
1
PIN #1 ID
(DATUM A)
(DATUM B)
0.10 M C A B
0.05 M C
NX b
10X
5
0.50
0.20
0.40
1.80
0.40
0.20
2.20
1.00
0.60
1.00
LAND PATTERN
10
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.45
0.50
0.55
-
A1
-
0.05
-
A3
0.127 REF
-
b
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
0.40 BSC
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N10
2
Nd
2
3
Ne
3
θ
0-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
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