参数资料
型号: ISL54065EVAL1Z
厂商: Intersil
文件页数: 14/15页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL54065
标准包装: 1
主要目的: 接口,2:1 多路复用器
嵌入式:
已用 IC / 零件: ISL54065
主要属性: 2 x SPDT 模拟开关
次要属性: 1.8 V ~ 6.5 V 电源
已供物品:
8
FN6583.2
November 3, 2009
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
FIGURE 8A. CLICK AND POP WAVEFORM
FIGURE 8B. CLICK AND POP TEST CIRCUIT
FIGURE 8. CLICK AND POP ELIMINATION
Test Circuits and Waveforms (Continued)
ANALYZER
RL
SIGNAL
GENERATOR
V+
C
0V OR V+
NO OR NC
COM
IN
GND
Signal direction through switch is reversed, worst case values
are recorded.
*50
Ω SOURCE
V+
C
0V OR V+
NO OR NC
COM
IN
GND
VNX
V1
rON = V1/100mA
100mA
0V OR V+
ANALYZER
V+
C
NO1 OR NC1
SIGNAL
GENERATOR
RL
GND
INX
COM1
50
Ω
NC
COM2
NC2 OR NO2
Signal direction through switch is reversed, worst case values
are recorded.
*50
Ω SOURCE
V+
C
GND
NO OR NC
COM
IN
IMPEDANCE
ANALYZER
0V OR V+
COM is connected to NO or NC
during ON capacitance measurement.
tD
VDC
VINx*
*VINx waveform for Click and Pop Elimination on NOx terminal.
For Click and Pop Elimination on NCx terminal invert INx.
tD = 200ms measured at 50% points.
0V
tD
CLICK AND POP
CIRCUITRY
RL
220F
INx
COMx
NCx
NOx
VDC
ISL54065
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