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参数资料
| 型号： | ISL5416EVAL |
| 厂商： | Intersil Corporation |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | 四通道可编程宽带下变频器 |
| 文件页数： | 14/71页 |
| 文件大小： | 2013K |
| 代理商： | ISL5416EVAL |
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14
Back-end Routing
FIR Filter Blocks
There are two programmable FIR filters in each channel.
The main function of the first filter, FIR1, is to reduce the CIC
output sample rate and maximize the efficiency of the
second filter, FIR2. FIR2 provides the final filtering for the
channel of interest. FIR1 can compute up to 32 taps and has
programmable 20-bit coefficients, 20-bit data inputs, and 24-
bit outputs. FIR2 can compute up to 64 taps and has
programmable 20-bit coefficients, 20-bit input data, and 24-
bit output data. FIR1 can compute 4 filter taps per clock and
FIR2 can compute 8. All of the available taps can be utilized
if the overall decimation through the CIC and FIRs is 8 or
more. The impulse response of each FIR can be symmetric
or asymmetric. The decimation for the each FIR is
programmable from 1 to 8.
To maximize dynamic range, the output bit width of the CIC
and each FIR is 24 bits. A programmable gain stage is
provided before each FIR to compensate for losses in
preceding stages and round to the 20-bit FIR input bit width.
Gains of 1, 2, 4, or 8 can be programmed. Saturation logic is
provided to prevent overflow.
FIR1 includes a half-band filter mode where a fixed center
coefficient of 0.5 is added and the zero valued half-band
coefficients are skipped in the computation. This allows FIR1
to compute a 15-tap half-band filter in two clock cycles or a
31-tap half-band filter in four clock cycles.
NOTE:
When loading halfband coefficients, the coefficients must be
centered around the fixed center coefficient, e.g. if there are
23 taps, three compute clocks are required, there are 11 on
either side of the center and multiplier 1 computes C0, C2,
C4, multiplier 2 C6, C8, C10, etc.
If there are 19 coefficients, multiplier 2 computes C4, C6, C8
and multiplier 1 computes Z, C0, and C2, i.e. an extra zero
valued coefficient must be added at each end of the
coefficient set to center the coefficients at the fixed
coefficient.
The filters will have unity gain if the sum of all coefficients is
equal to 1 for coefficient bit weighting 2
0
. . . 2
-19
MAG
AGC
LOOP
FILTER
FIR2
MUX
AGC
MULT
M
U
X
FROM
CIC
GAIN
I
Q
FIR1
G
G
EXTERNAL AGC GAIN
MAG
DETECT
1X
2X
4X
8X
1X
2X
4X
8X
FIFO
IHBF
HOIF
UP TO 32 TAPS
4 TAPS/CLK
HBF MODE
8 TAPS/CLK
UP TO 64 TAPS
CIC
BYPASS
CASCADED
CHANNELS
I
Q
ISL5416
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL5416EVAL1 | 功能描述:EVALUATION PLATFORM FOR ISL5416 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| ISL5416KI | 功能描述:上下转换器 QUAD WIDEBAND DOWN CONVERTER, 256 CABGA RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| ISL5416KIZ | 制造商:Intersil Corporation 功能描述:LEAD-FREE QUAD WIDEBAND DOWN CONVERTER, 256 CABGA - Trays 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL QUAD DIGITAL DOWNCONVER 制造商:Intersil 功能描述:QD WIDEB& DWN CNVRTR 256 CABGA |
| ISL54200 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
| ISL54200_07 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
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