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参数资料
| 型号： | ISL5416EVAL |
| 厂商： | Intersil Corporation |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | 四通道可编程宽带下变频器 |
| 文件页数： | 5/71页 |
| 文件大小： | 2013K |
| 代理商： | ISL5416EVAL |
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5
JTAG
TDO
O
Test data out
TDI
I
PULL UP
Test data in.
TMS
I
PULL UP
Test mode select.
TCLK
I
PULL DOWN
Test clock.
TRST
I
PULL UP
Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and
there is enough board noise, the JTAG port might get into an unexpected state and stop
communications with the part
OUTPUTS
Aout(15:0)
O
Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section. See Table 24.
Bout(15:0)
O
Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Cout(15:0)
O
Parallel Data Output bus C. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Dout(15:0)
O
Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Below is the table of the serial output bits allocation for DOUT.
Eout(15:0)
O
A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses.
CLKO1
O
Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is
programmable.
CLKO2/
INTRPT
O
Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second
clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt
from one or more channels for a sequenced read (FIFO-like) mode.
See register GWA = 0000h, bit
13.
Pin Descriptions
(Continued)
NAME
TYPE
INTERNAL
PULL-UP/DOWN
DESCRIPTION
SERIAL OUTPUT BITS ALLOCATION
SER. OUTPUT A
SER. OUTPUT B
SER. OUTPUT C
SER. OUTPUT D
SCLKX *
DOUT0
DOUT4
DOUT8
DOUT12
SSYNCX *
DOUT1
DOUT5
DOUT9
DOUT13
SD1X *
DOUT2
DOUT6
DOUT10
DOUT14
SD2X *
DOUT3
DOUT7
DOUT11
DOUT15
* X denotes A, B, C, D as appropriate
ISL5416
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL5416EVAL1 | 功能描述:EVALUATION PLATFORM FOR ISL5416 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| ISL5416KI | 功能描述:上下转换器 QUAD WIDEBAND DOWN CONVERTER, 256 CABGA RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| ISL5416KIZ | 制造商:Intersil Corporation 功能描述:LEAD-FREE QUAD WIDEBAND DOWN CONVERTER, 256 CABGA - Trays 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL QUAD DIGITAL DOWNCONVER 制造商:Intersil 功能描述:QD WIDEB& DWN CNVRTR 256 CABGA |
| ISL54200 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
| ISL54200_07 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
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