参数资料
型号: ISL54500IRUZ-T
厂商: Intersil
文件页数: 11/13页
文件大小: 0K
描述: IC SWITCH SPDT SGL 6UTDFN
产品培训模块: Patient Monitoring and Diagnostic Equipment Solutions
标准包装: 1
功能: 开关
电路: 1 x SPDT
导通状态电阻: 5 欧姆
电压电源: 单电源
电压 - 电源,单路/双路(±): 1.8 V ~ 5.5 V
电流 - 电源: 20nA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-UFDFN
供应商设备封装: 6-UTDFN(1.2x1.0)
包装: 标准包装
其它名称: ISL54500IRUZ-TDKR
7
FN6549.2
November 9, 2009
Detailed Description
The ISL54500 is a bi-directional, single pole/double
throw (SPDT) analog switch that offers precise
switching capability from a single 1.8V to 5.5V supply
with low ON-resistance (5Ω) and high speed operation
(tON = 22ns, tOFF = 15ns). The device is especially
well suited for portable battery powered equipment
due to its low operating supply voltage (1.8V), low
power consumption (0.11W), low leakage currents
(300nA max) and small TDFN and SOT-23 packages.
The low ON-resistance and rON flatness provide very
low insertion loss and distortion to application that
require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil
recommends adding a 100Ω resistor in series with the
V+ power supply pin of the ISL54050 IC
(see Figure 8).
During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate
currents can be generated in the IC that can trigger
parasitic SCR structures to turn ON, creating a low
impedance path from the V+ power supply to ground.
This will result in a significant amount of current flow in
the IC, which can potentially create a latch-up state or
permanently damage the IC. The external V+ resistor
limits the current during this over-stress situation and
has been found to prevent latch-up or destructive
damage for many over voltage transient events.
Under normal operation, the sub-microamp IDD
current of the IC produces an insignificant voltage drop
across the 100Ω series resistor resulting in no impact
to switch operation or performance.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
ANALYZER
RL
SIGNAL
GENERATOR
V+
C
0V OR V+
NO OR NC
COM
IN
GND
V+
C
VINL OR VINH
NO OR NC
COM
IN
GND
VNX
V1
100mA
rON = V1/I1
*
I1
* I1 = 10mA AT V+ = 1.8V
0V or V+
ANALYZER
V+
C
NO OR NC
SIGNAL
GENERATOR
RL
GND
IN1
COM
NC OR NO
50
Ω
V+
C
GND
NO OR NC
COM
IN
IMPEDANCE
ANALYZER
VINL OR VINH
ISL54500
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