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参数资料
| 型号： | ISL5585ECR-TK |
| 厂商： | Intersil |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC SLIC RINGING 3.3V VOB 32-QFN |
| 标准包装： | 1,000 |
| 功能： | 用户线路接口概念（SLIC） |
| 电路数： | 1 |
| 电源电压： | 3.3V |
| 功率（瓦特）： | 305mW |
| 工作温度： | 0°C ~ 75°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（7x7） |
| 包装： | 带卷 (TR) |
| 包括： | 均衡和不均衡振铃，振铃声信号发生器，热关机，带警报指示器 |
18
When the input signal at VRS is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
Ringing Input
The ringing input, VRS, is a high impedance input. The high
impedance allows the use of low value capacitors for AC
coupling the ring signal. The VRS input is enabled only
during the ringing mode, therefore a free running oscillator
may be connected to VRS at all times.
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95VP-P. Hence, the
maximum signal swing at VRS to achieve full scale ringing is
approximately 2.4VP-P. The low signal levels are compatible
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator.
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
RRT and CRT. The resistor RRT sets the trip threshold and the
capacitor CRT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, Pr, and the silent interval power, Ps.
The terms tR and tS represent the cadence. The ringing
interval is tR and the silent interval is tS . The typical cadence
ratio tR:tS is 1:2.
The quiescent power of the device in the ringing mode is
defined in Equation 58.
The total power during the ringing interval is the sum of the
quiescent power and loading power:
For sinusoidal waveforms, the average current, IAVG, is
defined in Equation 60.
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Unbalanced Ringing
The ISL5585GCM offers Unbalanced Ringing mode (010).
This feature accommodates some Analog PBX Trunk Lines
that require the Tip terminal to be held near ground for the
duration of the ringing bursts. The Tip terminal is offset to
0V’s with an internal current source that is applied to the
inverting input of the Tip amplifier. This reduces the
differential ringing gain to 40V/V. The Ring terminal will
center at Vbh/2 and swing from -Vbh to ground. As in
Balanced Ringing, off hook detection is accomplished by
sensing the peak current and comparing it to a preset
threshold. This allows the same sensing, comparing and
threshold circuitry to be used in both Ringing modes. This
mode of operation does not require any additional external
components.
Forward Loop Back
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600
terminating resistor has a tolerance of
±20%. The device is
intended to operate from only the low battery during this
mode.
Architecture
P
RNG
P
r
t
r
t
r
t
s
+
--------------
×
P
s
t
s
t
r
t
s
+
--------------
×
+
=
(EQ. 57)
P
rQ
()
V
BH
I
BHQ
×
V
BL
I
BLQ
×
V
CC
I
CCQ
×
++
=
(EQ. 58)
P
r
P
rQ
()
V
BH
I
AVG
×
V
RMS
2
Z
REN
R
LOOP
+
------------------------------------------
–
+
=
(EQ. 59)
I
AVG
2
π
---
VRMS
2
×
Z
REN
R
LOOP
+
------------------------------------------
=
(EQ. 60)
ISL5585
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相关代理商/技术参数 |
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| ISL5585ECRZ-TK | 功能描述:IC SLIC RINGING 3.3V VOB 32-QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
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