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| 型号： | ISL58115CRZ-EVAL |
| 厂商： | Intersil |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL58115CRZ |
| 标准包装： | 1 |
| 系列： | * |
ISL58115
Applications Information
APC System Overview
As the laser heats up (or ages) its output power declines relative
to the applied current, so some form of power control is required.
The laser is optically coupled to a photo-diode, so that the laser’s
optical output can be measured. Laser optical output power is
controlled by comparing the externally applied control voltage
with the voltage produced by the IV-amplifier which converts the
photo-diode’s output current into a voltage. Since the calibrated
During calibration mode, the internal servo control will bring the
laser diode output power level to match the voltage control level
set by VC voltage.
Horizontal edge detection
When HPSB is low, the output current is set by RPS. Asserting
HPSB low overrides both channel data inputs. HPSB should not
be asserted low during a calibration cycle. When HPSB is low, the
desired output current I RPS is governed by the following
equation:
I RPS = 40 × ----------------------- × ----------------
gain is stored as a digital number in a register, the ISL58115
exhibits none of the time-dependent droop that is seen in most
printers' laser diode drivers. This is of particular importance
RPS 1.05V
CalDAC R SET
(EQ. 3)
during high dot/inch graphics modes where the line may be
slowed down very significantly to allow 2400 dots per inch or
even more.
Fixed-Threshold Laser Bias Control
When a laser is driven from below threshold to well above
threshold, it exhibits a few cycles of a damped oscillation. The
amplitude of this oscillation is minimized when the laser is kept
above threshold. The “fixed” bias mode is set by asserting a logic
Low on the SLPEN pin. To set the laser bias threshold currents,
I BIAS , connect external resistors from RBIAS pins to GND. Figure
1 shows value of R BIAS corresponding to desired bias current.
100
10
where the CalDAC setting (from the last write power calibration)
ensures laser temperature and aging compensation. The
CalDAC’s units are ohms. Full scale is about 380 ? and CalDAC is
defined as CalDAC = 255/code*380 ? .
The horizontal sync pulse is meant to be a power level that
overrides VC calibration and sets the output current to a fixed
level.
Typical Application
Upon the printer being powered up, the lasers should be
calibrated. This would establish nominal light power outputs,
typically a few milliwatts at the laser regardless of the ambient
temperature and also any laser aging.
Once everything is ready for printing, the paper is in position and
the mirror-motor is phase-locked then the print line(s) can be
written. Before, or after, the beam is over the photo-sensitive
drum, each laser can be re-calibrated. This continual re-
calibration will compensate for any temperature drift of the laser,
especially at the initial warming up period.
Since the calibrated gain is stored as a digital number in a
1
0.1
1
10
register, the ISL58115 exhibits no time-dependent droop. With
no droop to degrade performance the only limitation now is the
R BIAS (k Ω )
FIGURE 1. R BIAS vs BIAS CURRENT
Scaling External Resistors
R SET is used to scale the switching output current. Switching
output current, I SW , is the function of VC and R SET .
lasers' own temperature change along the line. This in turn can
be compensated for to some extent by adding a data-dependent
compensation signal to the analog VCx input pin. It may be found
that in fast draft modes for example, that the laser temperature
change is sufficiently small that many lines can be written before
the laser(s) need to be re-calibrated. If the printed page has a low
enough duty cycle, no re-calibration may be needed at all.
I SW = I SW Gain × ? ---------------- – --------------- ?
? R R ?
DAC SET
VC 2
(EQ. 1)
The ISL58115 has analog voltage inputs to allow the laser power
level to be adjusted during the line. Typically this would be driven
Where I SW Gain = ~17, R DAC = 400 Ω .
R BIAS sets bias threshold current. Figure 1 exhibits the
relationship between I BIAS and R BIAS . The bias current is set as
Equation 2:
with a PWM, low bandwidth signal to compensate for the
differing beam path length as the beam is swept from one side
of the page to the other.
Undervoltage, overcurrent and over-temperature error conditions
are ORed together and made available on the ERRB pin.
I BIAS = BiasChannelGain × ------------------------------------
InternalVref
R BIAS
(EQ. 2)
Note on Illegal Logic Combination
Where BiasChannelGain = ~40, InternalVref = 1.0V.
Controlling the Sampling
The switching levels are sampled independently. This can be
done during the “off-paper” period.
7
In normal use, CALB going low (active) without DIS being low
(active) would be meaningless. Likewise with HPSB going low
(active). Therefore, a combination of these should be avoided at
all times. If this combination is applied, the chip will not work
properly. To exit this mode, either set CALB to Low or/and DIS to
Hi.
FN6671.1
July 29, 2013
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