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参数资料
| 型号： | ISL5829INZ |
| 厂商： | Intersil |
| 文件页数： | 4/13页 |
| 文件大小： | 0K |
| 描述： | IC CONV DUAL 12BIT 3.3V 48-LQFP |
| 标准包装： | 250 |
| 功能： | D/A 转换器 |
| RF 型： | 手机，GSM，EDGE，WCDMA |
| 次要属性： | 双路 12 位 |
| 封装/外壳： | 48-LQFP |
| 包装： | 托盘 |
ISL5829
Pin Descriptions
PIN NO.
11, 19, 26
13, 24
28
27
10
20
14, 23
12, 25
PIN NAME
AGND
A VDD
CLK
DGND
D VDD
FSADJ
NC
ICOMP, QCOMP
PIN DESCRIPTION
Analog ground.
Analog supply (+2.7V to +3.6V).
Clock input.
Connect to digital ground.
Digital supply (+2.7V to +3.6V).
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x V FSADJ /R SET .
Not internally connected. Recommend no connect.
Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1 μ F capacitor.
1-6, 29-40,
43-48
ID11-ID0, QD11-QD0 Digital data input ports. Bit 11 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
15, 22
16, 21
17
18
7, 8, 41, 42
9
IOUTA, QOUTA
IOUTB, QOUTB
REFIO
REFLO
NC
SLEEP
4
Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1 μ F cap to ground when internal reference is enabled.
Connect to analog ground to enable internal 1.2V reference or connect to AV DD to disable internal reference.
No connect (NC). Not internally connected. No termination required, may be used for device migration to
higher resolution DACs.
Connect to digital ground or leave floating for normal operation. Connect to DV DD for sleep mode.
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