参数资料
型号: ISL5927INZ
厂商: Intersil
文件页数: 4/13页
文件大小: 0K
描述: IC DAC 14BIT CMOS DUAL 48LQFP
标准包装: 250
位数: 14
数据接口: 并联
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 275 mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
输出数目和类型: *
采样率(每秒): *
12
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
RDIFF
ISL5927
RLOAD
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
OUTA
OUTB
VOUT = (2 x OUTA x REQ)V
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
1:1
REQ = 0.5 x (RLOAD//RDIFF)
AT EACH OUTPUT
FIGURE 14. ALTERNATIVE OUTPUT LOADING
ISL5927
OUTA
OUTB
VOUT = (2 x OUTA x REQ)V
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB
AT EACH OUTPUT
RLOAD
RDIFF
RA
RB
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
Timing Diagram
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
IOUT
50%
tPW1
tPW2
tSU
tHLD
tSU
tPD
tHLD
D13-D0
W0
W1
W2
W3
OUTPUT=W0
OUTPUT=W1
tPD
OUTPUT=W-1
ISL5927
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