参数资料
| 型号： | ISL59446IRZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 3/13页 |
| 文件大小： | 0K |
| 描述： | IC AMP MUX 4:1 500MHZ 32-QFN |
| 标准包装： | 1 |
| 应用： | 4:1 多路复用器-放大器 |
| 电路数： | 3 |
| -3db带宽： | 620MHz |
| 转换速率： | 1600 V/µs |
| 电流 - 电源： | 44mA |
| 电流 - 输出 / 通道： | 135mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1235 (CN2011-ZH PDF) |
| 其它名称： | ISL59446IRZ-T7DKR |
11
FN6261.2
June 5, 2012
back-loaded controlled impedance interconnect. Load
resistor RL is still required but can be 500
Ω or greater,
resulting in a much smaller attenuation factor.
Control Signals
S0, S1, ENABLE, HIZ - These are binary coded, TTL/CMOS
compatible control inputs. The S0, S1 pins select the inputs.
All three amplifiers are switched simultaneously from their
respective inputs. The ENABLE pin is used to disable the part
to save power, and the HIZ pin to set the output stage in a
high impedance state. For control signal rise and fall times
less than 10ns the use of termination resistors close to the
part may be necessary to prevent reflections and to minimize
transients coupled to the output.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
to the V+ and V- supplies. In addition, a dV/dT- triggered
clamp is connected between the V+ and V- pins, as shown in
the Equivalent Circuits 1 through 4 section of the Pin
Description table. The dV/dT triggered clamp imposes a
maximum supply turn-on slew rate of 1V/s. Damaging
currents can flow for power supply rates-of-rise in excess of
1V/s, such as during hot plugging. Under these conditions,
additional methods should be employed to ensure the rate of
rise is not exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 30) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
HIZ State
An internal pull-down resistor ensures the device will be
active with no connection to the HIZ pin. The HIZ state is
established within approximately 20ns (Figure 26) by placing
a logic high (>2V) on the HIZ pin. If the HIZ state is selected,
the output impedance is ~1000
Ω (Figure 8). The supply
current during this state is same as the active state.
ENABLE and Power-Down States
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The power-down state is established within
approximately 200ns (Figure 24), if a logic high (>2V) is
placed on the ENABLE pin. In the power-down state, the
output has no leakage but has a large variable capacitance
(on the order of 15pF), and is capable of being back-driven.
Under this condition, large incoming slew rates can cause
fault currents of tens of mA. Therefore, the parallel connection
of multiple outputs is not recommended unless the application
can tolerate the limited power-down output impedance.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip line
are used.
V+
V-
V+
V-
V+
V-
LOGIC
CONTROL
GND
IN0
IN1
S0
OUT
EXTERNAL
CIRCUITS
SCHOTTKY
PROTECTION
V+
V-
POWER
GND
SIGNAL
LOGIC
V+ SUPPLY
V- SUPPLY
DECOUPLING
CAPS
FIGURE 29. SCHOTTKY PROTECTION CIRCUIT
ISL59446
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