参数资料
| 型号： | ISL59451IRZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 7/17页 |
| 文件大小： | 0K |
| 描述： | IC AMP MUX TRIPLE 4:1 DC 32-QFN |
| 标准包装： | 1,000 |
| 应用： | 4:1 多路复用器-放大器 |
| 电路数： | 3 |
| -3db带宽： | 240MHz |
| 转换速率： | 930 V/µs |
| 电流 - 电源： | 45mA |
| 电流 - 输出 / 通道： | 125mA |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
15
FN6253.0
September 24, 2007
Therefore, if VREF is set to 0V (GND); VOUT = 15mV, and
the DC voltage stored on CX1 is ~1.6V.
The CX1 capacitor value is chosen from the system
requirements. A typical DC-restore application using an
NTSC video horizontal sync to drive the CLAMP pin will
result in a 62s hold time. The typical input bias current to
the video amplifier is 1.2A, so for a 62s hold time, and a
0.01F capacitor, the output voltage drift is 7.5mV in one
line. The restore amplifier can provide a typical source
current of 860A to charge capacitor CX1, so with a 1.2s
sampling time, the output can be corrected by 36mV in each
line.
Using a smaller value of CX1 increases both the voltage that
can be corrected, as well as the droop while being held.
Likewise, using a larger value of CX1, reduces the correction
and droop voltages. A sample of charging and droop rates
are shown in Table 2.
Figure 36 shows the test setup for measuring the DC
Restore’s response to an input DC step shown in Figures 21
and 22.
FIGURE 36. DC STEP RESPONSE
AC Design Considerations
High speed current-feed amplifiers are sensitive to
capacitance at the inverting input and output terminals.
Capacitance at the output terminal increases gain peaking
and overshoot. The AC response of the ISL59451 is
optimized for a total output capacitance of 2.1pF with a load
of 150
Ω (Figure 35A). When PCB trace capacitance and
component capacitance exceed 2pF, overshoot becomes
strongly dependent on the input pulse amplitude and slew
rate. Increasing levels of output capacitance reduce stability,
resulting in increased overshoot and settling time.
PC board trace length (LCRIT) should be kept to a minimum
in order to minimize output capacitance. At 500MHz, trace
lengths approaching 1” begin exhibiting transmission line
behavior and may cause excessive ringing if controlled
impedance traces are not used. Figure 35B shows the
optimum inter-stage circuit when the total output trace length
is less than the critical length of the highest signal frequency.
As a general rule of thumb the trace lengths should be less
than one-tenth of the wavelength of the highest frequency
component in the signal. Equation 6 shows an approximate
way to calculate LCRIT in meters.
c = speed of light (3 x 10^8 m/s)
fMAX = maximum frequency component
εR = relative dielectric of board material (e.g. FR4 = 4.2)
For applications where inter-stage distances are long but
pulse response is not critical, capacitor CS can be added to
low values of RS to form a low-pass filter to dampen pulse
overshoot. This approach avoids the need for the large gain
correction required by the -6dB attenuation of the
back-loaded controlled impedance interconnect. Load
resistor RL is still required but can be 500Ω or greater,
resulting in a much smaller attenuation factor.
For applications where pulse response is critical and where
inter-stage distances exceed LCRIT, the circuit shown in
capacitance seen by the amplifier output to the trace
capacitance betweeen the output pin and the resistor.
Therefore, RS should be placed as close to the ISL59451
output pin as possible. For inter-stage distances much greater
should be used with controlled impedance PCB lines, with RS
and RL equal to the controlled impedance.
Control Signals
S0, S1, HIZ, CLAMP, and AV2 are binary coded, TTL/CMOS
compatible control inputs. The S0, S1 pins select the inputs.
All three amplifiers are switched simultaneously from their
respective inputs. When HIZ is pulled high, it puts the outputs
in a high-impedance state and disconnects the video inputs.
TABLE 2. TABLE OF CHARGE STORAGE CAPACITOR VS
DROOP CHARGING RATES (NOTE)
CAP VALUE
(nF)
DROOP IN
62s
(mV)
CHARGE IN
1.2s
(mV)
CHARGE IN
4s
(mV)
10
7.5
103
344
33
2.3
32.5
103
100
0.75
10.3
34
V
DROOP
I
B
CAP Value
-----------------------------
Line Time
Sample Time
–
()
×
=
(EQ. 4)
V
CHARGE
I
CLAMP
CAP Value
-----------------------------
Sample Time
()
×
=
(EQ. 5)
75
Ω
75
Ω
500
Ω
0.1F
NTSC
VIDEO
1Hz SQUARE WAVE
150
Ω
OUTPUT
CLAMP
ISL59451
NTSC HSYNC
TIMING
L
CRIT
c
10
f
MAX
ε
R
×
--------------------------------------------
≤
(EQ. 6)
ISL59451
相关PDF资料 |
PDF描述 |
|---|---|
| ISL59452IRZ-T7 | IC AMP MUX TRIPLE 4:1 DC 32-QFN |
| ISL59481IRZ | IC MUX AMP DUAL 500MHZ 48-QFN |
| ISL59482IRZ | IC MUX AMP DUAL 500MHZ 48-QFN |
| ISL59483IRZ | IC MUX AMP DUAL 500MHZ 48-QFN |
| ISL59605IRZ-T7A | IC VIDEO EQUALIZER 20-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL59452 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple 4:1 Single Supply Video Multiplexing Amplifier |
| ISL59452IRZ | 功能描述:IC AMP TRIPLE MUX 250MHZ 32-QFN RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 应用:TFT-LCD 面板：VCOM 驱动器 输出类型:满摆幅 电路数:1 -3db带宽:35MHz 转换速率:40 V/µs 电流 - 电源:3.7mA 电流 - 输出 / 通道:1.3A 电压 - 电源，单路/双路(±):9 V ~ 20 V，±4.5 V ~ 10 V 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽）裸露焊盘 供应商设备封装:8-uMax-EP 包装:管件 |
| ISL59452IRZ-T7 | 功能描述:IC AMP MUX TRIPLE 4:1 DC 32-QFN RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 应用:TFT-LCD 面板：VCOM 驱动器 输出类型:满摆幅 电路数:1 -3db带宽:35MHz 转换速率:40 V/µs 电流 - 电源:3.7mA 电流 - 输出 / 通道:1.3A 电压 - 电源，单路/双路(±):9 V ~ 20 V，±4.5 V ~ 10 V 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽）裸露焊盘 供应商设备封装:8-uMax-EP 包装:管件 |
| ISL59481 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual, 500MHz Triple, Multiplexing Amplifiers |
| ISL59481_07 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual, 500MHz Triple, Multiplexing Amplifiers |
发布紧急采购，3分钟左右您将得到回复。