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| 型号： | ISL6115ACBZ-T |
| 厂商： | Intersil |
| 文件页数： | 5/10页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR POWER DIST 12V 8-SOIC |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 10.2 V ~ 13.8 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
ISL6115A
Electrical Specifications
V DD = 12V, T A = T J = full temperature range, Unless Otherwise Specified.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNITS
CURRENT REGULATION DURATION/POWER GOOD
C TIM Charging Current
C TIM Fault Pull-Up Current (Note 6)
Current Limit Time-Out Threshold
Voltage
Power Good Pull Down Current
C TIM _ichg0
C TIM _Vth
PG_Ipd
V CTIM = 0V
CTIM Voltage
V OUT = 0.5V
17.2
-
1.6
-
20.5
20
1.8
8
25
-
2.1
-
μA
mA
V
mA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Description and Operation
The ISL6115A is targeted for +12V single power supply
distribution control for generic hot swap switching
applications.
This ICs features a highly accurate programmable
current regulation (CR) level with programmable time
delay to latch-off, and programmable soft-start
turn-on ramp all set with a minimum of external
passive components. It also includes severe OC
protection that immediately shuts down the MOSFET
switch should a rapid load current transient such as
with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, it has an
UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once
the IC is biased, monitoring and reporting any UV
condition on the ISEN pin.
this time, the time-out capacitor, on CTIM pin is
charged with a 20μA current source and the controller
enters the current limit time to latch-off period. The
length of the current limit time to latch-off duration is
set by the value of a single external capacitor (see
Table 2) for C TIM capacitor value and resulting
nominal current limited time-out to latch-off duration
placed from the CTIM pin (pin 6) to ground. The
programmed current level is held until either the OC
event passes or the time-out period expires. If the
former is the case then the N-Channel MOSFET is fully
enhanced and the C TIM capacitor is discharged. Once
C TIM charges to ~1.8V signaling that the time-out
period has expired, an internal latch is set whereby
the FET gate is quickly pulled to 0V turning off the
N-Channel MOSFET switch, isolating the faulty load.
TABLE 1. R ISET PROGRAMMING RESISTOR VALUE
Upon initial power-up, the IC can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail
voltage directly to the load for true hot swap capability.
The PWRON pin must be pulled low for the device to
R ISET RESISTOR
10k Ω
4.99k Ω
2.5k Ω
1.25k Ω
NOMINAL CR VTH
200mV
100mV
50mV
25mV
isolate the power supply from the load by holding the
external N-Channel MOSFET off. With the PWRON pin
held high or floating the IC will be in true hot swap
mode. In both cases the IC turns on in a soft-start
mode protecting the supply rail from sudden inrush
current.
At turn-on, the external gate capacitor of the
N-Channel MOSFET is charged with a 11μA current
source resulting in a programmable ramp (soft-start
turn-on). The internal ISL6115A charge pump supplies
the gate drive for the 12V supply switch driving that
gate to ~V DD +6.5V. Load current passes through the
external current sense resistor. When the voltage
across the sense resistor exceeds the user
programmed CR voltage threshold value, (see Table 1
for R ISET programming resistor value and resulting
nominal current regulation threshold voltage, V CR )
the controller enters its current regulation mode. At
5
NOTE: Nominal Vth = R ISET x 20μA.
TABLE 2. C TIM CAPACITOR VALUE
NOMINAL CURRENT LIMITED
C TIM CAPACITOR PERIOD
0.022μF 2ms
0.047μF 4.4ms
0.1μF 9.3ms
NOTE: Nominal time-out period = C TIM x 93k Ω .
This IC responds to a severe overcurrent load (defined
as a voltage across the sense resistor >150mV over
the OC Vth set point) by immediately driving the
N-Channel MOSFET gate to 0V in about 10μs. The gate
voltage is then slowly ramped up turning on the
N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
FN6855.1
April 23, 2010
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