参数资料
型号: ISL612XSEQEVAL1
厂商: Intersil
文件页数: 4/23页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL612XSEQ
标准包装: 1
主要目的: 电源管理,电源监控器/跟踪器/序列发生器
嵌入式:
已用 IC / 零件: ISL6123,ISL6124,ISL6126,ISL6127,ISL6128,ISL6130
主要属性: 4 通道电源定序器
次要属性: 欠压保护
已供物品: 板,IC 样品
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Descriptions
PIN NUMBER
PIN
ISL6123, ISL6124,
ISL6126,
NAME
V DD
GND
ENABLE_1/
ENABLE_1
ENABLE_2/
ENABLE_2
ISL6125
23
10
1
NC
ISL6130
23
10
1
NC
ISL6127
23
10
1
NC
ISL6128
23
10
1
11
DESCRIPTION
Chip Bias. Bias IC from nominal 1.5V to 5V.
Bias Return. IC ground.
Input to start on/off sequencing. Input to initiate start of programmed
sequencing of supplies on or off. Enable functionality disabled for 10ms after
UVLO is satisfied. ISL6123 and ISL6130 have ENABLE, and ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has two ENABLE
inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and
ENABLE_2 is for (C, D).
RESET
RESET_2
24
NC
24
NC
24
NC
24
9
RESET Output. RESET provides low signal 150ms after all GATEs are fully
enhanced. Delay is for stabilization of output voltages. RESET asserts low
upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. RESET
outputs are open-drain, N-channel FET and are guaranteed to be in correct
state for VDD down to 1V and are filtered to ignore fast transients on VDD and
UVLO_X.
RESET_2 only exists on ISL6128 for (C, D) group I/O.
UVLO_A
UVLO_B
UVLO_C
UVLO_D
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
DLY_OFF_A
DLY_OFF_B
DLY_OFF_C
DLY_OFF_D
GATE_A
GATE_B
GATE_C
GATE_D
20
12
17
14
21
8
16
15
18
13
3
4
2
5
6
7
20
12
17
14
18
13
3
4
2
5
6
7
20
12
17
14
2
5
6
7
20
12
17
14
21
8
16
15
18
13
3
4
2
5
6
7
Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout
referenced to an internal 0.633V reference. Filtered to ignore short (<30μs)
transients below programmed UVLO level.
Gate On Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-on using a capacitor to ground. Each capacitor charged with 1μA
10ms after turn-on initiated by ENABLE/ENABLE. Internal current source
provides delay to associated FET GATE turn-on.
Gate Off Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each
capacitor charged with 1μA internal current source to an internal reference
voltage, causing corresponding gate to be pulled down, thus turning off FET.
FET Gate Drive Output. Drives external FETs with 1μA current source to soft-
start ramp into load.
OUTPUT_A
OUTPUT_B
OUTPUT_C
OUTPUT_D
2 (ISL6125)
5 (ISL6125)
6 (ISL6125)
7 (ISL6125)
On ISL6125 only, these are ACTIVE open drain outputs that can be pulled up
to a maximum of VDD voltage.
SYSRST
22
22
System Reset I/O. As an input, allows for immediate and unconditional latch-off
of all GATE outputs when driven low. This input can also be used to initiate
programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input
signal on this pin being driven high to first GATE. As an output, when there is a UV
condition, this pin pulls low. If common to other SYSRST pins in a multiple IC
configuration, it causes immediate and unconditional latch-off of all other GATEs
on all other ISL612X sequencers.
GND
NC
EPAD
9, 19
EPAD
8, 9, 11,
EPAD
3, 4, 8, 9,
EPAD
19, 22
Ground. Die Substrate. Can be left floating.
No Connect
15, 16,
11, 13,
19, 21, 22 15,16,18,
19, 21
4
FN9005.12
September 26, 2012
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