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| 型号： | ISL612XSEQEVAL1 |
| 厂商： | Intersil |
| 文件页数： | 8/23页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL612XSEQ |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ISL6123，ISL6124，ISL6126，ISL6127，ISL6128，ISL6130 |
| 主要属性： | 4 通道电源定序器 |
| 次要属性： | 欠压保护 |
| 已供物品： | 板，IC 样品 |
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
DLY_OFF pins. Once all four UVLO inputs and ENABLE are
satisfied for 10ms (t delEN_LO) , the four DLY_ON capacitors
are simultaneously charged with 1μA current sources to the
DLY_Vth level of 1.27V. As each DLY_ON pin reaches the
DLY_Vth level, its associated GATE turns on, with a 1μA
source current to the charge pump voltage (VQP) of V DD +
5.3V. Thus, all four GATEs sequentially turn on in the user
defined order. Once at DLY_Vth, the DLY_ON pins discharge
so they are ready when next needed.
After the entire turn-on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay (T RSTdel ) is started to ensure stability, after
which the RESET output is released to go high.
After turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~30μs), it is considered a fault.
RESET and SYSRST are pulled low, and all GATEs are
simultaneously also pulled low. In this mode, the GATEs are
pulled low with 88mA.
Normal shutdown mode is entered when no UVLO is violated
and ENABLE is deasserted. When ENABLE is deasserted,
RESET is immediately asserted and pulled low. Next, all four
shutdown ramp capacitors on the DLY_OFF pins are charged
with a 1μA source. When any ramp-capacitor reaches
DLY_Vth, a latch is set, and a current is sunk on the
respective GATE pin to turn off its external MOSFET. When the
GATE voltage is approximately 0.6V, the GATE is pulled down
the rest of the way at a higher current level. Each individual
external FET is thus turned off, which removes the voltages
from the load in the user programmed sequence.
The ISL6123 and ISL6124 have the same functionality,
except for the ENABLE active polarity; the ISL6124 has an
ENABLE input. Additionally, the ISL6123 and ISL6130 also
have an ultra low-power sleep state when ENABLE is low.
The ISL6125 has the same personality as the ISL6124, but
instead of charged-pump-driven GATE outputs, it has
open-drain outputs that can be pulled up to a maximum of
V DD .
The ISL6126 and ISL6130 are different in that their on
sequence is not time determined but voltage determined.
Each of the four channels operate independently. Once the IC
is biased and any one of the UVLO inputs is greater than the
0.63V internal reference, and the ENABLE input is also
satisfied, the associated GATE for the satisfied UVLO input
turns on.
In turn, the other UVLO inputs must be satisfied for the
associated GATEs to turn on. After a period of 160ms
(T RSTdel ) once all GATEs are fully on (GATE voltage = VQP),
RESET is released to go high.
The UVLO inputs can be driven by either a previously
turned-on output rail offering a voltage-determined sequence
or by logic signal inputs. Any subsequent UVLO level that is
less than its programmed level pulls the associated GATE and
RESET output low (if previously released) but does not
latch-off the other GATEs.
Predetermined turn-off is accomplished by deasserting
ENABLE. This causes RESET to latch low and all four GATE
8
outputs to follow the programmed turn-off sequence,
similarly to the ISL6124.
The ISL6127 is a 4-channel sequencer pre-programmed for
A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and
ENABLE inputs are satisfied for ~10ms, the sequencing
starts. The next GATE in the sequence starts to ramp up once
the previous GATE has reached ~VQP-1V. After a period of
160ms (T RSTdel ) after the last GATE is at VQP, the RESET
output is deasserted. If any UVLO is unsatisfied, RESET is
pulled low, SYSRST is pulled low, and all GATEs are
simultaneously turned off. When ENABLE is signaled high,
the D GATE starts to pull low. Once below 0.6V, the next GATE
starts to pull low, and so on, until all GATEs are at 0V.
Unloaded, this turn-off sequence completes in <1ms.
This variant offers a lower cost and size implementation
because the external delay capacitors are not used. Because
the delay capacitors are not used, this IC cannot delay the
start of subsequent GATEs. Thus, necessary stabilization or
system housekeeping need to be considered.
The ISL6128 is a 4-channel device that groups the four
channels into two groups of two channels each. Each group
of A, B and C, D, has its own ENABLE and RESET I/O pins. All
four UVLO and both ENABLEs must be satisfied for
sequencing to start . The A, B group turns on first, 10ms after
the second ENABLE is pulled low, with A then B turning on,
followed by C then D.
Once the preceding GATE = VQP, the next DLY_ON pin starts to
charge its capacitor; thus, all four GATEs turn on. Approximately
160ms after D GATE = VQP, the RESET output is released to go
high. Once any UVLO is unsatisfied, only the related group’s
RESET and two GATEs are pulled low. The related EN input must
be cycled for the faulted group to be turned on again.
Normal shutdown is invoked by signaling both ENABLE inputs
high, which causes the two related GATEs to shut down in
reverse order from turn-on. DLY_X capacitors adjust the delay
between GATES during turn-on and turn-off, but not the order.
During bias up, the RESET output is guaranteed to be in the
correct state, with V DD lower than 1V.
Upon power-up, the SYSRST pin follows V DD with a weak
internal pull-up. It is both an input and an output connection and
can provide two functions. As an input, if it is pulled low, all
GATEs are unconditionally shut off, and RESET pulls low
(Figure 8). This input can also be used as a no-wait enabling
input. If all inputs (ENABLE and UVLO) are satisfied, it does not
wait through the ~10ms enable delay to initiate DLY_ON
capacitor charging when released to go high. As an output, it is
useful when implementing multiple sequencers in a design
needing simultaneous shutdown, as with a kill switch across all
sequencers. Once any UVLO is unsatisfied longer than tFIL, the
related SYSRST pulls low. It also pulls low all other SYSRST
inputs that are on a common connection. By doing so, it
unconditionally shuts down all outputs across multiple
sequencers.
Except for the ISL6128 after a fault, restart of the turn-on
sequence is automatic, once all requirements are met. This
allows for no interaction between the sequencer and a controller
IC, if desired. The ENABLE and RESET I/O do allow for a higher
FN9005.12
September 26, 2012
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相关代理商/技术参数 |
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|---|---|
| ISL612XSEQEVAL1Z | 功能描述:EVALUATION BOARD ISL612XSEQ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器 嵌入式:否 已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池 次要属性:状态 LED 已供物品:板 |
| ISL6130 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Power Sequencing Controllers |
| ISL6130IRZA | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6130IRZA-T | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6130IRZA-TS2378 | 制造商:Intersil Corporation 功能描述: |
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