参数资料
型号: ISL6144EVAL1Z
厂商: Intersil
文件页数: 18/30页
文件大小: 0K
描述: EVALUATION BOARD ISL6144 ORING
标准包装: 1
主要目的: 电源管理,O 环控制器/负荷分载
已用 IC / 零件: ISL6144
已供物品:
ISL6144
hold off and other internal bias and reference circuitry. The
charge pump circuitry starts functioning as the input voltage
at the V IN pin reaches a value around 8V. The gate voltage
depends on the load current (as explained in previous
sections), The maximum gate voltage will be clamped to a
maximum of V GQP when load current becomes too high to
be handled with 20mV across the source-drain terminals.
Overall, it takes less than 1ms to reach the load-dependent
final gate voltage value. Note that the Input voltage cannot
be hot swapped and has to rise slowly. A rise time of at least
1ms is recommended for the voltage at VIN pin.
V IN = 48V; RESISTIVE LOAD = 4A, C GSEXT = 33n F
V IN1 , V G1 ,I IN1 and HV REF(VZ) WAVEFORMS
V IN = 12V; RESISTIVE LOAD = 5A, C GSEXT = 33nF
I IN1
5A/DIV
V G1
5V/DIV
V IN1
5V/DIV
V OUT
5V/DIV
HV REF(Vz)
5V/DIV
I IN1
2A/DIV
4A
0A
V G1
10V/DIV
V IN1
10V/DIV
FIGURE 19. FIRST FEED V IN1 START-UP (12V CASE)
The start-up tests were done with the addition of an external
gate to source capacitor to demonstrate start-up time with a
total equivalent gate-source capacitance around 39nF.
SECOND (CONSECUTIVE) FEED START-UP
WHEN V IN REACHES ~ 8V AND HVREF REACHES
3V to 4V, GATE CHARGE PUMP ACTION STARTS
V IN1 , V G1 , I IN1 and V OUT WAVEFORMS
In this case, the ISL6144 for the second (consecutive) feed
(U4) already has output bias voltage as the first parallel feed
has been turned on and V OUT is present on the common bus.
As V IN2 rises, V G2 rises with it (V G2 is GATE2 voltage with
respect to GND). When V IN2 approaches V IN1 value, Gate 2 is
turned. Second feed gate turn-on is faster than the first feed as
the HVREF capacitor (C 3 ) is already charged.The second or
consecutive power supply to be started can be turned on faster
0A
I IN1
5A/DIV
4A
than the first power supply, a rise time of at least 200μs of the
second rail is recommended.
V IN = 48V; RESISTIVE LOAD = 4A, C GS(EXT) = 33n F
V OUT
20V/DIV
I IN2
2A/DIV
V OUT
20V/DIV
V G1
20V/DIV
V IN1
20V/DIV
IN THIS CASE GATE VOLTAGE IS MEASURED
BETWEEN GATE2 AND GND
WHEN V IN REACHES ~ 8V
AND HVREF REACHES 3V TO 4V
GATE CHARGE PUMP ACTION STARTS
FIGURE 18. FIRST FEED V IN1 START-UP (48V CASE)
SECOND GATE TURNS ON ONLY
WHEN V IN2 REACHES V IN1
POWER SUPPLY
RELATED DELAY
V G2
20V/DIV
V IN2
20V/DIV
FIGURE 20. SECOND (CONSECUTIVE) FEED V IN2 START-UP
18
FN9131.7
October 6, 2011
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ISL6144IRZA-T 功能描述:IC CTRLR MOSFET HV ORING 20-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - O 圈控制器 系列:- 标准包装:1,000 系列:- 应用:电池备份,工业/汽车,大电流开关 FET 型:- 输出数:5 内部开关:是 延迟时间 - 开启:100ns 延迟时间 - 关闭:- 电源电压:3 V ~ 5.5 V 电流 - 电源:250µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-SOIC(0.154",3.90mm 宽) 供应商设备封装:16-SOIC N 包装:带卷 (TR)
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