参数资料
型号: ISL6144IRZA-T
厂商: Intersil
文件页数: 9/30页
文件大小: 0K
描述: IC CTRLR MOSFET HV ORING 20-QFN
标准包装: 6,000
应用: 电信/数据通信系统
FET 型: N 沟道
输出数: 1
内部开关:
延迟时间 - 开启: 1ms
延迟时间 - 关闭: 250ns
电源电压: 9 V ~ 75 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-VQFN 裸露焊盘
供应商设备封装: 20-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
ISL6144
load current. Power loss across the ORing devices is as
shown in Equation 6:
On the other hand, the most common failures caused by
diode ORing include open circuit and short circuit failures. If
P loss ( D 2 ) = I OUT ? V F = 40A ? 0.5V = 20W
(EQ. 6)
one of these diodes (Feed A) has failed open, then the other
Feed B will provide all of the power demand. The system will
P loss ( M2 ) = ( I OUT ) ? r DS ( ON ) = ( 40A ) ? 5m Ω = 8W
P loss ( FET ) = ? ----------------- ? ? r DS ( ON )
I LOAD 2
? N + 1 ?
2 2
This shows that worst-case failure scenario has to be
accounted for when choosing the ORing MOSFET. In this
case we need to use two MOSFETs in parallel per feed to
reduce overall power dissipation and prevent excessive
temperature rise of any single MOSFET. Another alternative
would be to choose a MOSFET with lower r DS(ON ).
The final choice of the N-Channel ORing MOSFET depends
on the following aspects:
1. Voltage Rating: The drain-source breakdown voltage
V DSS has to be higher than the maximum input voltage
including transients and spikes. Also the gate to source
voltage rating has to be considered, The ISL6144
maximum Gate charge voltage is 12V, make sure the
used MOSFET has a maximum V GS rating >12V.
2. Power Losses: In this application the ORing MOSFET is
used as a series pass element, which is normally fully
enhanced at high load currents; switching losses are
negligible. The major losses are conduction losses, which
depend on the value of the on-state resistance of the
MOSFET r DS(ON) , and the per feed load current. For an
N + 1 redundant system with perfect current sharing, the
per feed MOSFET losses are as shown in Equation 7:
(EQ. 7)
The r DS(ON) value also depends on junction temperature;
a curve showing this relationship is usually part of any
MOSFET’s data sheet. The increase in the value of the
r DS(ON) over temperature has to be taken into account.
3. Current handling capability, steady state and peak, are
also two important parameters that must be considered.
The limitation on the maximum allowable drain current
comes from limitation on the maximum allowable device
junction temperature. The thermal board design has to be
able to dissipate the resulting heat without exceeding the
MOSFET’s allowable junction temperature.
Another important consideration when choosing the ORing
MOSFET is the forward voltage drop across it. If this drop
approaches the 0.41V limit, which is used in the V OUT fault
monitoring mechanism, then this will result in a permanent
fault indication. Normally the voltage drop would be chosen
not to exceed a value around 100mV.
“ISL6144 + ORing FET” vs “ORing Diode” Solution
continue to operate without any notification of this failure,
reducing the system to a single point of failure. A much more
dangerous failure is where the diode has failed short. The
system will continue to operate without notification that the
short has occurred. With this failure, transients and failures
on Feed B propagate to Feed A. Also, this silent short failure
could pose a significant safety hazard for technical
personnel servicing these feeds.
“ISL6144 + ORing FET” vs “Discrete ORing FET”
Solution
If we compare the ISL6144 integrated solution to discrete
ORing MOSFET solutions, the ISL6144 wins in all aspects.
The main ones are: PCB real estate saving, cost savings,
and reduction in the MTBF of this section of the circuit as the
overall number of components is reduced.
In brief, the solution offered by this IC enhances power
system performance and protection while not adding any
considerable cost. This solution provides both a PCB board
real estate savings and a simple to implement integrated
solution.
Setting the External HS Comparator Threshold
Voltage
In general, paralleled modules in a redundant power system
have some form of active current sharing, to realize the full
benefit of this scheme, including lower operating
temperatures, lower system failure rate, and better transient
response when load step is shared. Current sharing is
realized using different techniques; all of these techniques
will lead to similar modules operating under similar
conditions in terms of switching frequency, duty cycle, output
voltage and current. When paralleled modules are current
sharing, their individual output ripple will be similar in
amplitude and frequency and the common bus will have the
same ripple as these individual modules and will not cause
any of the turn-off mechanisms to be activated, as the same
ripple will be present on both sensing nodes (V IN and
V OUT ). This would allow setting the high speed comparator
threshold (V TH(HS) ) to a very low value. As a starting point, a
V TH(HS) of 50mV could be used, the final value of this TH
will be system dependent and has to be finalized in the
system prototype stage. If the gate experiences false turn-off
due to system noise, the V TH(HS) has to be increased.
The reverse current peak can be estimated as:
I reverseP = -------------------------------------------------------------------------
“ISL6144 + ORing FET” solution is more efficient, which will
result in simplified PCB and thermal design. It will also
eliminate the need for a heat sink for the ORing diode. This
V TH ( HS ) + V SD + V OS ( HS )
r DS ( ON )
(EQ. 8)
will result in cost savings. In addition, the ISL6144 solution
provides a more flexible, reliable and controllable ORing
functionality and protects against system fault scenarios
(refer to “Fault Detection Block” on page 8).
9
where:
V SD is the MOSFET forward voltage drop.
V OS(HS) is the voltage offset of HS Comparator.
FN9131.7
October 6, 2011
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