参数资料
型号: ISL6144IV-T
厂商: Intersil
文件页数: 19/30页
文件大小: 0K
描述: IC CTRLR MOSFET HV ORING 16TSSOP
标准包装: 2,500
应用: 电信/数据通信系统
FET 型: N 沟道
输出数: 1
内部开关:
延迟时间 - 开启: 1ms
延迟时间 - 关闭: 250ns
电源电压: 9 V ~ 75 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
ISL6144
I IN1
Gate Fast Turn-off Test
During normal operation, the ISL6144 provides gate drive
voltage for the ORing MOSFET when the Input voltage
exceeds the output voltage. The current flows in the forward
direction from the input to the output. Now, what happens if
the input voltage drops quickly below the output voltage as a
result of a failure on the input sourcing power supply while
the MOSFET remained on? The answer is: If the MOSFET is
kept on, current starts to flow in the reverse direction from
the output to the input. Of course this is not desired nor
acceptable. It will lead to effectively shorting the output and
causing an overall system failure. In order to block this
reverse current, the ISL6144 senses the voltage at both VIN
and COMP pins (this is V OUT voltage reduced by a resistor
programmable threshold (V TH(HS ), it is programmed to
55mV on the EVAL board and could be adjusted by
changing R 1 , R 4 values for both feeds. If V IN drops below
COMP (V OUT - V TH(HS ), the High Speed Comparator turns
off the gate of the ORing MOSFET very quickly, the gate pull
down current I PDH is 2A. As a result the reverse current flow
is prevented. The maximum turn-off time is less than 300ns
when using an ORing MOSFET(s) with an equivalent gate-
source capacitance of 39nF (equivalent to Q TOT = 390nC at
V GS = 10V).
On the ISL6144EVAL1Z board, FDB3632 has an equivalent
t DELAY(HS) is the High Speed Comparator internal worst-
case time delay. The setup in Figure 17 can be used to
perform the Input dead-short test; a pulse generator is
connected between Gate-Source of Q SHORT1 (use pulse
mode single shot, set the frequency to <10Hz and pulse
width of approximately 10ms, t RISE = 1μs). Follow steps 1
through 5 in the two feed parallel operation section. Make
sure that both feeds operate in parallel current sharing
mode. Proceed with the short test by applying the single
pulse to the gate of Q SHORT1 . Once turned on, Q SHORT1
shorts V IN1 causing it to fall quickly (in less than 10 μ s).
Figures 21, 22 and 23 show the results for different
combinations of C GS1 and load current. Make sure to
connect the V IN1 shorting-MOSFET terminals as close as
possible to the V IN -GND (J4 to J6) terminals on the EVAL
board to minimize lead impedance and reduce parasitic
ringing.
V IN1 = V IN2 = 48V;
RESISTIVE LOAD = 6A, C gs(ext) = 33nF
2A/DIV
REVERSE CURRENT
V OUT
10V/DIV
gate-source capacitance of 8.4nF, some of the tests are
performed while an external gate to source capacitance is
added to demonstrate gate current sink capability.
V IN1 = V IN2 = 48V; RESISTIVE LOAD = 4A, C GS(EXT) = 0n F
V G2
10V/DIV
V GS1
5V/DIV
0.1μs/DIV
V IN1
10V/DIV
I IN1
2A/DIV
V OUT
10V/DIV
FIGURE 22. FAST SPEED TURN-OFF (MOSFET WITH
Q TOT = 8.4nc) AND 33nF EXTERNAL C GS
V GS1
2V/DIV
0.1μs/DIV
REVERSE CURRENT DISSAPPEARS
WHEN GATE IS COMPLETELY OFF
I IN1
2A/DIV
V G2
10V/DIV
V IN1 = V IN2 = 48V;
RESISTIVE LOAD = 6A, C gs(ext) = 33nF
V OUT
10V/DIV
FIGURE 21. FAST SPEED TURN-OFF
(MOSFET WITH Q TOT = 8.4nc)
Worst-case turn-off time can be calculated as:
V GS1
5V/DIV
t toff ( WC ) = t DELAY ( HS ) + ? C GS ------------- ?
t toff ( WC ) = 50ns + ? 39nF ----------- ? = 284ns
? V GS ?
? I PDH ?
12V
? 2A ?
19
(EQ. 9)
0.1μs/DIV
FIGURE 23. FAST SPEED TURN-OFF (MOSFET WITH
Q TOT = 8.4nc) AND 33nF EXTERNAL C gs
FN9131.7
October 6, 2011
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