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| 型号： | ISL6144IV-T |
| 厂商： | Intersil |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MOSFET HV ORING 16TSSOP |
| 标准包装： | 2,500 |
| 应用： | 电信/数据通信系统 |
| FET 型： | N 沟道 |
| 输出数： | 1 |
| 内部开关： | 无 |
| 延迟时间 - 开启： | 1ms |
| 延迟时间 - 关闭： | 250ns |
| 电源电压： | 9 V ~ 75 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
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ISL6144
Detection of Power Feed Faults
The ISL6144 have two built-in mechanisms that monitor
voltages at VIN, VOUT and GATE pins. The first mechanism
monitors GATE with respect to VIN (with a 410mV threshold)
and the second mechanism monitors V IN with respect to VOUT
(with 370mV threshold). The open-drain FAULT pin will be
pulled low when any of the two above conditions is met.
Fault 3: MOSFET Gate to Source Dead Short
GATE voltage will be equal to V IN , GATE <V IN + 0.37V and a
fault is indicated.
V IN = 12V, FAULT PULLED TO +5V
FAULT
Some of the typical system faults detected by the ISL6144 are:
Fault 1: Open Fuse at the Input Side
V G1
5V/DIV
5V/DIV
V IN1
(Fuse has to be placed before the V IN tap, between the
power supply and the source of the ORing MOSFET), note
that the EVAL board does not have footprint for installing this
fuse. This feature can be tested by adding a fuse externally.
The open fuse results in near zero current flow through the
ORing MOSFET, only a very low current drawn by the IC
bias will flow. The voltage at VIN pin is effectively
disconnected from the power source and will start dropping
slowly. The regulated source-drain voltage falls below its
20mV level and the gate of the MOSFET is pulled down and
TIME SCALE
100μs/DIV
V OUT
5V/DIV
5V/DIV
turned off. GATE will become low and a fault is indicated with
internal built in delay (t FLT ).
Fault 2: Drain to Source Short
In this case V IN is shorted to V OUT , and in theory the voltage
drop across the shorted MOSFET terminals will be close to
0V. The Gate will be pulled down and a fault will be
indicated. The resistance of the Drain to Source short
multiplied by the Drain short current must be low enough to
result in V SD < V FWD_HR (refer to data sheet for worst case
values), Otherwise this fault cannot be detected.
FIGURE 27. MOSFET GATE TO SOURCE FAULT
Fault 4: ORing FET Off Condition
When V IN < V OUT , the Gate is off to block reverse current
flow. This means that if an ORing feed is not sharing current,
a fault will be indicated. Also if a feed (PS) is off while bias is
applied from V OUT to that feed, then a fault is also indicated.
Fault 5: MOSFET Gate to Drain Dead Short
In this case, the following condition will be violated GATE
<V IN + 0.37V and a fault is issued.
V IN = 12V, FAULT PULLED TO +5V
V IN = 12V, FAULT PULLED TO +5V
FAULT
V G1
5V/DIV
5V/DIV
V IN1
V G1
5V/DIV
FAULT
5V/DIV
TIME SCALE
100μs/DIV
V OUT
5V/DIV
5V/DIV
TIME SCALE
V OUT
5V/DIV
V IN1
5V/DIV
100μs/DIV
FIGURE 26. MOSFET DRAIN TO SOURCE FAULT
FIGURE 28. MOSFET GATE TO DRAIN FAULT
21
FN9131.7
October 6, 2011
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相关代理商/技术参数 |
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| ISL6144IVZA | 功能描述:IC CTRLR MOSFET ORING HV 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - O 圈控制器 系列:- 标准包装:1,000 系列:- 应用:电池备份，工业/汽车，大电流开关 FET 型:- 输出数:5 内部开关:是 延迟时间 - 开启:100ns 延迟时间 - 关闭:- 电源电压:3 V ~ 5.5 V 电流 - 电源:250µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC N 包装:带卷 (TR) |
| ISL6144IVZA-T | 功能描述:IC CTRLR MOSFET HV ORING 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - O 圈控制器 系列:- 标准包装:1,000 系列:- 应用:电池备份，工业/汽车，大电流开关 FET 型:- 输出数:5 内部开关:是 延迟时间 - 开启:100ns 延迟时间 - 关闭:- 电源电压:3 V ~ 5.5 V 电流 - 电源:250µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC N 包装:带卷 (TR) |
| ISL6144IVZA-T7A | 功能描述:热插拔功率分布 W/ANNEAL 16LD TSSOP ORING FET CONTRLR RoHS:否 制造商:Texas Instruments 产品:Controllers & Switches 电流限制: 电源电压-最大:7 V 电源电压-最小:- 0.3 V 工作温度范围: 功率耗散: 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Tube |
| ISL6146 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Low Voltage ORing FET Controller |
| ISL6146A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Low Voltage ORing FET Controller |
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